mpmc_pl175_sdr.s.svn-base

Spearhead2000 的 USB驱动程序

        AREA PL175_INIT_SDR, CODE, READONLY

	
;  /*****************************************************************************
;   *                                                                           *
;   * Defines for ST SDRAM delay line.                                          *
;   * The register are in apb_configuration                                     *   
;   *                                                                           *
;   *****************************************************************************/
APBCfgBase  	          EQU  0x12001000

SDRAM_OUTPUT_CLOCK_DELAY EQU  APBCfgBase + 0x050  ; // Base + 50
SDRAM_INTPUT_CLOCK_DELAY EQU  APBCfgBase + 0x054  ; // Base + 54
SDRAM_FB_CLOCK_SOURCE    EQU  APBCfgBase + 0x058  ; // Base + 58

;  /*****************************************************************************
;   *                                                                           *
;   * Defines for MPMC PL175.                                                  *
;   *                                                                           *
;   *****************************************************************************/
MPMCBase  	       EQU  0x1000C000

MPMCControl  	       EQU  MPMCBase + 0x000  ; Control register	   	       
MPMCStatus   	       EQU  MPMCBase + 0x004  ; Status register	   	       
MPMCConfig   	       EQU  MPMCBase + 0x008  ; Configuration register	       
MPMCDynamicControl     EQU  MPMCBase + 0x020  ; Dynamic memory control register
MPMCDynamicRefresh     EQU  MPMCBase + 0x024  ; Dynamic memory refresh timer
MPMCDynamicReadConfig  EQU  MPMCBase + 0x028  ; Read Data Configuration Register
MPMCDynamictRP         EQU  MPMCBase + 0x030  ; Dynamic memory precharge command period (tRP)
MPMCDynamictRAS        EQU  MPMCBase + 0x034  ; Dynamic memory precharge period (tRAS)
MPMCDynamictSREX       EQU  MPMCBase + 0x038  ; Dynamic memory self refresh exit time (tSREX)
MPMCDynamictWR         EQU  MPMCBase + 0x044  ; Dynamic memory write recovery time (tWR)
MPMCDynamictRC         EQU  MPMCBase + 0x048  ; Dynamic memory auto refresh and active command period (tRC)
MPMCDynamictRFC        EQU  MPMCBase + 0x04c  ; Dynamic memory auto refresh period, and auto refresh to active command period (tRFC)
MPMCDynamictXSR        EQU  MPMCBase + 0x050  ; Dynamic memory exit self refresh to active command time (tXSR)
MPMCDynamictRRD        EQU  MPMCBase + 0x054  ; Dynamic memory active bank A to active B time (tRRD)
MPMCDynamictMRD        EQU  MPMCBase + 0x058  ; Dynamic memory load mode register to active command time (tMRD)
MPMCDynamictCDLR       EQU  MPMCBase + 0x05c  ; Dynamic memory write to read command time (tCDLR)

MPMCStaticExtendedWait EQU  MPMCBase + 0x080  ; Static memory extended wait

; Dynamic memory bank registers  
MPMCDynamicConfig0     EQU  MPMCBase + 0x100  ; Dynamic memory configuration register
MPMCDynamicRasCas0     EQU  MPMCBase + 0x104  ; Dynamic memory RAS and CAS delay
MPMCDynamicConfig1     EQU  MPMCBase + 0x120  ; Dynamic memory configuration register
MPMCDynamicRasCas1     EQU  MPMCBase + 0x124  ; Dynamic memory RAS and CAS delay
MPMCDynamicConfig2     EQU  MPMCBase + 0x140  ; Dynamic memory configuration register
MPMCDynamicRasCas2     EQU  MPMCBase + 0x144  ; Dynamic memory RAS and CAS delay
MPMCDynamicConfig3     EQU  MPMCBase + 0x160  ; Dynamic memory configuration register
MPMCDynamicRasCas3     EQU  MPMCBase + 0x164  ; Dynamic memory RAS and CAS delay
 
; Static memory bank registers  
MPMCStaticConfig0      EQU  MPMCBase + 0x200  ; Static memory configuration register
MPMCStaticWaitWen0     EQU  MPMCBase + 0x204  ; Static memory write enable delay
MPMCStaticWaitOen0     EQU  MPMCBase + 0x208  ; Static memory output enable delay
MPMCStaticWaitRd0      EQU  MPMCBase + 0x20c  ; Static memory read delay
MPMCStaticWaitPage0    EQU  MPMCBase + 0x210  ; Static memory page mode read delay
MPMCStaticWaitWr0      EQU  MPMCBase + 0x214  ; Static memory write delay
MPMCStaticWaitTurn0    EQU  MPMCBase + 0x218  ; Static memory turn round delay

MPMCStaticConfig1      EQU  MPMCBase + 0x220  ; Static memory configuration register
MPMCStaticWaitWen1     EQU  MPMCBase + 0x224  ; Static memory write enable delay
MPMCStaticWaitOen1     EQU  MPMCBase + 0x228  ; Static memory output enable delay
MPMCStaticWaitRd1      EQU  MPMCBase + 0x22c  ; Static memory read delay
MPMCStaticWaitPage1    EQU  MPMCBase + 0x230  ; Static memory page mode read delay
MPMCStaticWaitWr1      EQU  MPMCBase + 0x234  ; Static memory write delay
MPMCStaticWaitTurn1    EQU  MPMCBase + 0x238  ; Static memory turn round delay

MPMCStaticConfig2      EQU  MPMCBase + 0x240  ; Static memory configuration register
MPMCStaticWaitWen2     EQU  MPMCBase + 0x244  ; Static memory write enable delay
MPMCStaticWaitOen2     EQU  MPMCBase + 0x248  ; Static memory output enable delay
MPMCStaticWaitRd2      EQU  MPMCBase + 0x24c  ; Static memory read delay
MPMCStaticWaitPage2    EQU  MPMCBase + 0x250  ; Static memory page mode read delay
MPMCStaticWaitWr2      EQU  MPMCBase + 0x254  ; Static memory write delay
MPMCStaticWaitTurn2    EQU  MPMCBase + 0x258  ; Static memory turn round delay

MPMCStaticConfig3      EQU  MPMCBase + 0x260  ; Static memory configuration register
MPMCStaticWaitWen3     EQU  MPMCBase + 0x264  ; Static memory write enable delay
MPMCStaticWaitOen3     EQU  MPMCBase + 0x268  ; Static memory output enable delay
MPMCStaticWaitRd3      EQU  MPMCBase + 0x26c  ; Static memory read delay
MPMCStaticWaitPage3    EQU  MPMCBase + 0x270  ; Static memory page mode read delay
MPMCStaticWaitWr3      EQU  MPMCBase + 0x274  ; Static memory write delay
MPMCStaticWaitTurn3    EQU  MPMCBase + 0x278  ; Static memory turn round delay

; AHB port registers  
MPMCAHBControl0        EQU  MPMCBase + 0x400  ; AHB control register 	
MPMCAHBStatus0         EQU  MPMCBase + 0x404  ; AHB status register  	
MPMCAHBTimeOut0        EQU  MPMCBase + 0x408  ; AHB time out register	
    
MPMCAHBControl1        EQU  MPMCBase + 0x420  ; AHB control register 	
MPMCAHBStatus1         EQU  MPMCBase + 0x424  ; AHB status register  	
MPMCAHBTimeOut1        EQU  MPMCBase + 0x428  ; AHB time out register	
    
MPMCAHBControl2        EQU  MPMCBase + 0x440  ; AHB control register 	
MPMCAHBStatus2         EQU  MPMCBase + 0x444  ; AHB status register  	
MPMCAHBTimeOut2        EQU  MPMCBase + 0x448  ; AHB time out register	
    
MPMCAHBControl3        EQU  MPMCBase + 0x460  ; AHB control register 	
MPMCAHBStatus3         EQU  MPMCBase + 0x464  ; AHB status register  	
MPMCAHBTimeOut3        EQU  MPMCBase + 0x468  ; AHB time out register	
    
MPMCAHBControl4        EQU  MPMCBase + 0x480  ; AHB control register 	
MPMCAHBStatus4         EQU  MPMCBase + 0x484  ; AHB status register  	
MPMCAHBTimeOut4        EQU  MPMCBase + 0x488  ; AHB time out register	
    
MPMCAHBControl5        EQU  MPMCBase + 0x4a0  ; AHB control register 	
MPMCAHBStatus5         EQU  MPMCBase + 0x4a4  ; AHB status register  	
MPMCAHBTimeOut5        EQU  MPMCBase + 0x4a8  ; AHB time out register	
    
MPMCTestControl        EQU  MPMCBase + 0xf00  ; Test control register

MPMCTestInput0         EQU  MPMCBase + 0xf20  ; Test input register
MPMCTestInput1         EQU  MPMCBase + 0xf24  ; Test input register

MPMCTestOutput         EQU  MPMCBase + 0xf40  ; Test output register

MPMCPeriphID4          EQU  MPMCBase + 0xfd0  ; Peripheral identification register bits [39:32]
MPMCPeriphID5          EQU  MPMCBase + 0xfd4  ; Reserved for peripheral identification register
MPMCPeriphID6          EQU  MPMCBase + 0xfd8  ; Reserved for peripheral identification register
MPMCPeriphID7          EQU  MPMCBase + 0xfdc  ; Reserved for peripheral identification register
MPMCPeriphID0          EQU  MPMCBase + 0xfe0  ; Peripheral identification register bits [7:0]
MPMCPeriphID1          EQU  MPMCBase + 0xfe4  ; Peripheral identification register bits [15:8]
MPMCPeriphID2          EQU  MPMCBase + 0xfe8  ; Peripheral identification register bits [23:16]
MPMCPeriphID3          EQU  MPMCBase + 0xfec  ; Peripheral identification register bits [31:24]
MPMCCellID0            EQU  MPMCBase + 0xff0  ; PrimeCell identification register bits [7:0]
MPMCCellID1            EQU  MPMCBase + 0xff4  ; PrimeCell identification register bits [15:8]
MPMCCellID2            EQU  MPMCBase + 0xff8  ; PrimeCell identification register bits [23:16]
MPMCCellID3            EQU  MPMCBase + 0xffc  ; PrimeCell identification register bits [31:24]


;/*
; *	 Company: Micron Technology, Inc.
; *	 Part Number: MT48LC32M16A2 (8Mb x 16 x 4 Banks)
; *	 Description: Micron 512Mb SDRAM
; *
; *	-- Timing Parameters for -75 (PC133) and CL = 3
; *	tAC	  : TIME    :=  5.4 ns;
; *	tHZ	  : TIME    :=  5.4 ns;
; *	tOH	  : TIME    :=  2.7 ns;
; *	tMRD	  : INTEGER :=  2;	    -- 2 Clk Cycles
; *	tRAS	  : TIME    := 44.0 ns;
; *	tRC	  : TIME    := 66.0 ns;
; *	tRCD	  : TIME    := 20.0 ns;
; *	tRFC	  : TIME    := 66.0 ns;
; *	tRP	  : TIME    := 20.0 ns;
; *	tRRD	  : TIME    := 15.0 ns;
; *	tWRa	  : TIME    :=  7.5 ns;     -- Auto precharge
; *	tWRm	  : TIME    := 15.0 ns;     -- Manual Precharge
; *
; *	tAH	  : TIME    :=  0.8 ns;
; *	tAS	  : TIME    :=  1.5 ns;
; *	tCH	  : TIME    :=  2.5 ns;
; *	tCL	  : TIME    :=  2.5 ns;
; *	tCK	  : TIME    :=  7.5 ns;
; *	tDH	  : TIME    :=  0.8 ns;
; *	tDS	  : TIME    :=  1.5 ns;
; *	tCKH	  : TIME    :=  0.8 ns;
; *	tCKS	  : TIME    :=  1.5 ns;
; *	tCMH	  : TIME    :=  0.8 ns;
; *	tCMS	  : TIME    :=  1.5 ns;
; *
; *	addr_bits : INTEGER := 13;
; *	data_bits : INTEGER := 16;
; *	col_bits  : INTEGER := 10
; *
; */

PL175_DYNAMIC_REFRESH_TIME_INIT   EQU  20 ;160
PL175_DYNAMIC_REFRESH_TIME        EQU (PL175_DYNAMIC_REFRESH_TIME_INIT + 5)

PL175_DYNAMIC_TRP_INIT            EQU 2  ; 2 * 10.42 ns > 20 ns (tRP)
PL175_DYNAMIC_TRAS_INIT           EQU 5  ; 5 * 10.42 ns > 44 ns (tRAS)
PL175_DYNAMIC_TSREX_INIT          EQU 6
PL175_DYNAMIC_TWR_INIT            EQU 1
PL175_DYNAMIC_TRC_INIT            EQU 7  ; 7 * 10.42 ns > 66 ns (tRC)
PL175_DYNAMIC_TRFC_INIT           EQU 7  ; 7 * 10.42 ns > 66 ns (tRFC)
PL175_DYNAMIC_TXSR_INIT           EQU 6
PL175_DYNAMIC_TRRD_INIT           EQU 2  ; 2 * 10.42 ns > 15 ns (tRRD)
PL175_DYNAMIC_TMRD_INIT           EQU 2
PL175_DYNAMIC_TCDLR_INIT          EQU 15
STATIC_EXTENDED_WAIT_INIT   	  EQU 50
STATIC_EXTENDED_WAIT        	  EQU (STATIC_EXTENDED_WAIT_INIT + 5)

PL175_RAS_CAS_LATENCY              EQU 0x0202 ; RAS LAT 2clk - CAS LAT 2clk
PL175_CONFIG0                      EQU 0x880  ; 64MB - SDR_SDRAM - NOT_WRITE_PROTECTED - (32Mx16)_4bnks_16BIText
PL175_CONFIG1                      EQU 0x680  ; 32MB - SDR_SDRAM - NOT_WRITE_PROTECTED - (16Mx16)_4bnks_16BIText
PL175_CONFIG2                      EQU 0x280  ;  8MB - SDR_SDRAM - NOT_WRITE_PROTECTED - (4Mx16)_4bnks_16BIText
PL175_CONFIG3                      EQU 0x480  ; 16MB - SDR_SDRAM - NOT_WRITE_PROTECTED - (8Mx16)_4bnks_16BIText

;PAUSE_POWER_UP_INIT         	  EQU 100  ; unit is  usec
;PAUSE_MEM_INIT              	  EQU 200  ; unit is  usec
;PAUSE_REFRESH_INIT          	  EQU 40   ; unit is  usec
PAUSE_POWER_UP_INIT         	  EQU 0  ; TEST - do not wait
PAUSE_MEM_INIT              	  EQU 0  ; TEST - do not wait
PAUSE_REFRESH_INIT          	  EQU 0  ; TEST - do not wait

PL175_ENDIANITY                   EQU 0  ; little endian
;PL175_DATA_STRATEGY               EQU 0x0101  ; SDR : (CMD_DELAYED + CAPTURE_NEGATIVE)
;PL175_DATA_STRATEGY               EQU 0x1212  ; SDR : (CMD_DELAYED + CAPTURE_POSITIVE)
;PL175_DATA_STRATEGY               EQU 0x1111 ; SDR : (CMD_DELAYED + CAPTURE_POSITIVE)
PL175_DATA_STRATEGY               EQU 0x0202  ; SDR : (CMD_DELAYED + CAPTURE_POSITIVE)
					      ; DDR : (CMD_DELAYED + CAPTURE_POSITIVE)


;uSDRAMModeConfig                  EQU 0x10042000  ; Mode reg is 0x21
;uSDRAMExtModeConfig               EQU 0x10000400   
uSDRAMModeConfig0                  EQU 0x00042000  ; Mode reg is 0x21 burst 2
uSDRAMExtModeConfig0               EQU 0x00000400   
;uSDRAMModeConfig1                  EQU 0x04042000  ; Mode reg is 0x21
uSDRAMModeConfig1                  EQU 0x04021000  ; Mode reg is 0x21 burst 2
uSDRAMExtModeConfig1               EQU 0x04000400   
;uSDRAMModeConfig2                  EQU 0x06042000  ; Mode reg is 0x21
uSDRAMModeConfig2                  EQU 0x06010800  ; Mode reg is 0x21 burst 2
;uSDRAMModeConfig2                  EQU 0x06010000  ; Mode reg is 0x20 burst 1
uSDRAMExtModeConfig2               EQU 0x06000400   
;uSDRAMModeConfig3                  EQU 0x06842000  ; Mode reg is 0x21
uSDRAMModeConfig3                  EQU 0x06821000  ; Mode reg is 0x21 burst 2
;uSDRAMModeConfig3                  EQU 0x06822000  ; Mode reg is 0x21 burst 4
uSDRAMExtModeConfig3               EQU 0x06800400   
;uDDRResetModeConfig               EQU 0x10000600




       EXPORT PL175_init_SDR

;/*************************************************************************/
;/*                                                                       */
;/* FUNCTION                                                              */
;/*                                                                       */
;/*      PL175_init_SDR                                                       */
;/*                                                                       */
;/* DESCRIPTION                                                           */
;/*                                                                       */
;/*      This routine initializes the DRAM Controller.                    */
;/*                                                                       */
;/* AUTHOR                                                                */
;/*                                                                       */
;/*      A. Visconti - ST Microelectronics                                */
;/*                                                                       */
;/*************************************************************************/
;VOID  PL175_init_SDR(void)
;{

    ; This code can be optimized using multiple store...
        
PL175_init_SDR ROUT

    MOV		v1, lr      ; Save lr

    ;/* Program the delay line (2.5 ns) */
    ;LDR     a1, =SDRAM_INTPUT_CLOCK_DELAY
    ;MOV     a2, #0x18
    ;STR     a2, [a1, #0]
    
    ;LDR     a1, =SDRAM_OUTPUT_CLOCK_DELAY
    ;MOV     a2, #0x18
    ;STR     a2, [a1, #0]
    
    ;/* Initial wait to ensure stable power, clock */
    ;apOS_TIMER_Wait( pInitial->PausePowerUp );
    LDR     a1, =PAUSE_POWER_UP_INIT
    ;BL      TimerWait
  
    ; /* Set up Normal Memory Map */
    ; ((PL175_sRegisters *) eBase)->Control = 
    ;	apBIT_BUILD( PL175_CONTROL_E, apPL175_DEVICE_ENABLED	     ) |
    ;	apBIT_BUILD( PL175_CONTROL_L, apPL175_OPERATE_NORMAL_MODE    );
    
    LDR     a2, =0x1
    LDR     a1, =MPMCControl