📄 smi.s.svn-base
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AREA SRAMC, CODE, READONLY ; /*****************************************************************************; * *; * Defines for Serial Flash Controller. *; * *; *****************************************************************************/;; /* SMEMC Base Address */; #define SRAMC ((UINT32 *) (0x1000F000));SMI_BASE EQU 0x1000F000; /* SRAMC Regions offset */; #define SMI_CR1 0x00; #define SMI_CR2 0x04; #define SMI_SR 0x08; #define SMI_TR 0x0C; #define SMI_RR 0x10;SMI_CR1 EQU 0x00SMI_CR2 EQU 0x04SMI_SR EQU 0x08SMI_TR EQU 0x0CSMI_RR EQU 0x10; /* SMI Registers values */; define SMI_CR1 to boot:; Reserved 2b00; WBM 1b0; SW 1b0; ADD_LENGHT 0x0; HOLD 0x00; FAST 1b0; PRESC 7b000 1000 -- 133MHz/8 = 16.63MHz; TCS 0x5; BE 0x1 ;CR1_BOOT_NO_FAST EQU 0x00000851 CR1_BOOT_FAST EQU 0x00008351 ; PRESC 7b000 0011; /* SMI Registers values */; define SMI_CR2 to boot:; Reserved 18x00000; BS 2b00; WEN 1b0; RSR 1b0; WCIE 1b0; TFIE 1b0; SEND 1b0; REC_LENGTH 3b000; Reserved 1b0; TRA_LENGTH 3b000 CR2_BOOT EQU 0x00000000 EXPORT SMI_init;/*************************************************************************/;/* */;/* FUNCTION */;/* */;/* void SMI_init (void) */;/* */;/* DESCRIPTION */;/* */;/* This routine initializes the SFLASH Controller. */;/* */;/* AUTHOR */;/* */;/* C. Parrella - ST Microelectronics */;/* */;/* CALLED BY */;/* */;/* INT_Initialize */;/* */;/* CALLS */;/* */;/* None */;/* */;/* INPUTS */;/* */;/* None */;/* */;/* */;/* OUTPUTS */;/* */;/* None */;/*************************************************************************/;VOID SMI_init(void);{SMI_init ROUT; The SMI controller is configured to booting from external Flash: ; boot <= '1' -- External memory boot from bank0; bank0_type <= '0' -- For Flash Address length (3 byte); In this way at reset the SMI is in Hardware Mode, both SMI_RR ; and SMI_TR must not be accessed. Into others registers we write ; the values at reset for read from external flash at max 20MHz from bank0; ; Load SMI Base Address ; LDR a1, =SMI_BASE ; /* ; * Bank 0 ; * 00001111 Rom0_SIZE : 1MB ; * 00 Reserved ; * 1 BANKENABLE: bank enabled ; * 010 C_LENGTH : Data phase length 0f 4 CLK ; * 01 B_SIZE : bus size 16 bit ; */ ; ; LDR a2, =SMI_CR1 LDR a3, =CR1_BOOT_FAST STR a3, [a1, a2] ; /* ; * Disable bank1 ; */ ; ; LDR a2, =SMI_CR2 LDR a3, =CR2_BOOT STR a3, [a1, a2] ; return(); ; MOV pc, lr;} END
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