📄 file.log.svn-base
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1c1< AREA PL175_INIT, CODE, READONLY---> AREA PL175_INIT, CODE, READONLY21c21< MPMCBase EQU 0x2000A000---> MPMCBase EQU 0xf0000000168c168< PL175_DYNAMIC_REFRESH_TIME_INIT EQU 20 ;160---> PL175_DYNAMIC_REFRESH_TIME_INIT EQU 20 ;160 181c181< STATIC_EXTENDED_WAIT_INIT EQU 50---> STATIC_EXTENDED_WAIT_INIT EQU 50 200,201c200,201< uSDRAMModeConfig EQU 0x10042000 ; Mode reg is 0x21< uSDRAMExtModeConfig EQU 0x10000400 ---> uSDRAMModeConfig EQU 0 ; Mode reg is 0x21> uSDRAMExtModeConfig EQU 0 592c592,617< TIMER EQU 0x30000000---> ;TIMER EQU 0xf1000000> ;> ;> ;; timer2 registers> ;TIMER_CONTROL2 EQU TIMER + 0x100> ;TIMER_STATUS2 EQU TIMER + 0x104> ;TIMER_INT_ACK2 EQU TIMER + 0x104> ;TIMER_COMPARE2 EQU TIMER + 0x108> ;TIMER_COUNT2 EQU TIMER + 0x10C> ;TIMER_REDG_CAPT2 EQU TIMER + 0x110 ;not used> ;TIMER_FEDG_CAPT2 EQU TIMER + 0x114> ;> ;; Detailed Registers Naming> ;TIMER_PRESCAL EQU 0x00F > ;TIMER_MODE EQU 0x010 > ;TIMER_ENAB EQU 0x020 > ;TIMER_NO_CAPT EQU 0x000> ;TIMER_RE_CAPT EQU 0x040> ;TIMER_FE_CAPT EQU 0x080> ;TIMER_RF_CAPT EQU 0x0C0> ;TIMER_MATCH_INT EQU 0x100 > ;TIMER_FEDG_INT EQU 0x200 > ;TIMER_REDG_INT EQU 0x400 > ;TIMER_MATCH EQU 0x001 > ;TIMER_FEDG EQU 0x002 > ;TIMER_REDG EQU 0x004 594,618d618< < ; timer2 registers< TIMER_CONTROL2 EQU TIMER + 0x100< TIMER_STATUS2 EQU TIMER + 0x104< TIMER_INT_ACK2 EQU TIMER + 0x104< TIMER_COMPARE2 EQU TIMER + 0x108< TIMER_COUNT2 EQU TIMER + 0x10C< TIMER_REDG_CAPT2 EQU TIMER + 0x110 ;not used< TIMER_FEDG_CAPT2 EQU TIMER + 0x114< < ; Detailed Registers Naming< TIMER_PRESCAL EQU 0x00F < TIMER_MODE EQU 0x010 < TIMER_ENAB EQU 0x020 < TIMER_NO_CAPT EQU 0x000< TIMER_RE_CAPT EQU 0x040< TIMER_FE_CAPT EQU 0x080< TIMER_RF_CAPT EQU 0x0C0< TIMER_MATCH_INT EQU 0x100 < TIMER_FEDG_INT EQU 0x200 < TIMER_REDG_INT EQU 0x400 < TIMER_MATCH EQU 0x001 < TIMER_FEDG EQU 0x002 < TIMER_REDG EQU 0x004 < 629,665c629< ; a1 keeps the 'val' parameter< LDR a2, =TIMER_CONTROL2 ; keep the timer_control2 register address in a2< < ; turn the timer off (just in case ...)< ; GPTCntl->TIMER_2_CONTROL_REG &= ~GPT_ENAB; < MOV a4, #0x0< STR a4, [a2, #0]< < ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;< ; Enable timer2, but do not use the prescaler (unit is 100 ns)< ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;< ; GPTCntl->TIMER_2_CONTROL_REG |= GPT_ENAB | GPT_AUTO_RELOAD; < MOV a4, #0x20< STR a4, [a2, #0]< < ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;< ; Wait until timer2 reaches 'val'< ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;< < MOV a3, #10< MUL a4, a1, a3 ; Since 'val' isn usec unit but timer2 unit is in 100 nsec, we< ; need to multiply it by ten.< < MOV a1, a4< < LDR a3, =TIMER_COUNT2 ; keep the timer_count2 register address in a3< loop< LDR a4, [a3, #0]< CMP a4, a1< BLT loop< < ; turn the timer off< ; GPTCntl->TIMER_2_CONTROL_REG &= ~GPT_ENAB; < MOV a4, #0x0< STR a4, [a2, #0]< < ; return();---> ; return();668c632< --->
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