mpmc_pl175_ddr.s.svn-base

Spearhead2000 的 USB驱动程序

//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_MCC,  apPL175_CLKOUT_ENABLED )    |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_I,    apPL175_INIT_MODE )	      |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_DC,   apPL175_DLL_HANDSHAKING_DISABLED )  |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_DE,   apPL175_DLL_HANDSHAKING_DISABLED )  |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_DP,   apPL175_NORMAL_OPERATION )  |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_NRP,  apPL175_RP_HIGH )	      |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_RPV,  apPL175_RPVHH_NORMAL );
*/

    LDR     a2, =0x008b
    LDR     a1, =MPMCDynamicControl
    STR     a2, [a1, #0]

/*    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;
//    ; Program Mode and ExtMode registers for dynamic #0
//    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    
//    ; * If the Extended Mode Register has been set , perform additional read	         
//    ;  * to program the SDRAM extended mode register.				         
//    ;  * For DDR memories should disable DLL.					         
//    ;  *									         
//    ; if( pInitial->uSDRAMExtModeConfig[ 0 ] != 0 )				         
//    ; {										         
//    ; 	 (void) *((volatile UWORD32 *) pInitial->uSDRAMExtModeConfig[ I ]);	         
//    ; }*/

    LDR     a1, =uSDRAMExtModeConfig
    CMP     a1, #0x0
    LDRNE   a2, [a1, #0]

/*    ; * Perform read to each device. 						         
//    ;  * The address of the read is used to configure the SDRAM memories mode register.   
//    ;  * For DDR memories should reset DLL.					         
//    ;  *									         
//    ; if( pInitial->uSDRAMModeConfig[ 0 ] != 0 ) 				         
//    ; {										         
//    ; 	 (void) *((volatile UWORD32 *) pInitial->uSDRAMModeConfig[ I ]);	         
//    ; }										         
*/

    LDR     a1, =uSDRAMModeConfig
    CMP     a1, #0x0
    LDRNE   a2, [a1, #0]
            
/*    ; * Wait **/
/*    ; apOS_TIMER_Wait( pInitial->PauseMemInit );*/
    LDR     a1, =PAUSE_MEM_INIT
    BL      TimerWait

/*    ;* Issue PALL *
//    ;((PL175_sRegisters *) eBase)->DynamicControl =
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_CE,   apPL175_CLK_DRIVEN_HIGH )   |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_CS,   apPL175_CLKOUT_RUNS ) |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_SR,   apPL175_NORMAL_MODE )       |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_SRMCC,  apPL175_CLKOUT_SREF_RUN )	|
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_IMCC, apPL175_NCLKOUT_ENABLED )   |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_MCC,  apPL175_CLKOUT_ENABLED )    |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_I,    apPL175_INIT_PALL )	      |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_DC,   apPL175_DLL_HANDSHAKING_DISABLED )  |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_DE,   apPL175_DLL_HANDSHAKING_DISABLED )  |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_DP,   apPL175_NORMAL_OPERATION )  |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_NRP,  apPL175_RP_HIGH )	      |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_RPV,  apPL175_RPVHH_NORMAL );
*/

    LDR     a2, =0x010b
    LDR     a1, =MPMCDynamicControl
    STR     a2, [a1, #0]

/*    ; Wait */
/*    ; apOS_TIMER_Wait( pInitial->PauseRefresh );*/
    LDR     a1, =PAUSE_REFRESH_INIT
    BL      TimerWait

/*    ;* Select command write mode */
//    ;((PL175_sRegisters *) eBase)->DynamicControl =
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_CE,   apPL175_CLK_DRIVEN_HIGH )   |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_CS,   apPL175_CLKOUT_RUNS ) |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_SR,   apPL175_NORMAL_MODE )       |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_SRMCC,  apPL175_CLKOUT_SREF_RUN )	|
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_IMCC, apPL175_NCLKOUT_ENABLED )   |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_MCC,  apPL175_CLKOUT_ENABLED )    |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_I,    apPL175_INIT_MODE )	      |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_DC,   apPL175_DLL_HANDSHAKING_DISABLED )  |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_DE,   apPL175_DLL_HANDSHAKING_DISABLED )  |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_DP,   apPL175_NORMAL_OPERATION )  |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_NRP,  apPL175_RP_HIGH )	      |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_RPV,  apPL175_RPVHH_NORMAL );*/

    LDR     a2, =0x008b
    LDR     a1, =MPMCDynamicControl
    STR     a2, [a1, #0]

/*    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;
//    ; Reset Mode config for dynamic #0
//    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    
//    ; * Perform read to each device.						        
//    ;  * required for DDR memories to remove reset DLL bit 			        
//    ;  * The address of the read is used to configure the SDRAM memories mode register 
//    ;  *									        
//    ; if( pInitial->uDDRResetModeConfig[ 0 ] != 0 )				        
//    ; {										        
//    ; 	 (void) *((volatile UWORD32 *) pInitial->uDDRResetModeConfig[ I ]);	        
//    ; }										        
//    ;     
*/

    LDR     a1, =uDDRResetModeConfig
    CMP     a1, #0x0
    LDRNE   a2, [a1, #0]
    
/*    ;* Select Normal mode, clear Dynamic memory clock enable */
//    ;((PL175_sRegisters *) eBase)->DynamicControl =
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_CE,   apPL175_CLK_DRIVEN_HIGH )   |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_CS,   apPL175_CLKOUT_RUNS ) |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_SR,   apPL175_NORMAL_MODE )       |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_SRMCC,  apPL175_CLKOUT_SREF_RUN )	|
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_IMCC, apPL175_NCLKOUT_ENABLED )   |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_MCC,  apPL175_CLKOUT_ENABLED )    |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_I,    apPL175_INIT_NORMAL )       |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_DC,   apPL175_DLL_HANDSHAKING_DISABLED )  |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_DE,   apPL175_DLL_HANDSHAKING_DISABLED )  |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_DP,   apPL175_NORMAL_OPERATION )  |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_NRP,  apPL175_RP_HIGH )	      |
//    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_RPV,  apPL175_RPVHH_NORMAL );*/

    LDR     a2, =0x000b
    LDR     a1, =MPMCDynamicControl
    STR     a2, [a1, #0]

/*    ;* Initialise Static Memory registers for all banks *
//    ;for( I = 0; I < 4; I++)      
//    ;{
//    ;    if(pInitial->StaticConfigEnable[ I ] == TRUE)
//    ;    { 
//    ;       apPL175_StaticMemoryConfigSet( oId, I, &pInitial->sConfig.sStaticConfig[ I ] );
//    ;    }
//    ;}

//    ;* Program MPMCStaticExtendedWait register*
//    ;((PL175_sRegisters *) eBase)->StaticExtendedWait = pInitial->sConfig.StaticExtendedWait;
*/




/*    ;  return();*/
/*    ;*/
    MOV		pc, v1     /* ; Restore lr*/
      
/*;}*/

/*;-------------------------------------------------------------------------------
//; USE TIMER2 for MPMC PL175 programming
//;-------------------------------------------------------------------------------
*/

#define TIMER    0x12001000


/*; timer2 registers*/
#define TIMER_CONTROL2  TIMER + 0x100
#define TIMER_STATUS2   TIMER + 0x104
#define TIMER_INT_ACK2  TIMER + 0x104
#define TIMER_COMPARE2  TIMER + 0x108
#define TIMER_COUNT2      TIMER + 0x10C
#define TIMER_REDG_CAPT2  TIMER + 0x110      /* ;not used*/
#define TIMER_FEDG_CAPT2  TIMER + 0x114

/*;	Detailed Registers Naming*/
#define TIMER_PRESCAL 0x00F	
#define TIMER_MODE    0x010	
#define TIMER_ENAB    0x020	
#define TIMER_NO_CAPT 0x000
#define TIMER_RE_CAPT 0x040
#define TIMER_FE_CAPT 0x080
#define TIMER_RF_CAPT 0x0C0
#define TIMER_MATCH_INT  0x100	
#define TIMER_FEDG_INT   0x200	
#define TIMER_REDG_INT   0x400	
#define TIMER_MATCH      0x001   
#define TIMER_FEDG       0x002   
#define TIMER_REDG       0x004   

/*;
//; This routine uses the TIMER2 to wait for 'val' microseconds.
//; Please note that at this stage the timer is clocked with 10MHz clock 
//; (cycle time is 100 nsec).
//;
//;VOID  TimerWait(UINT32 val)
//;{
*/

TimerWait:

/*    ; a1 keeps the 'val' parameter*/
    LDR     a2, =TIMER_CONTROL2  /*; keep the timer_control2 register address in a2*/

/*    ; turn the timer off (just in case ...)*/
/*    ; GPTCntl->TIMER_2_CONTROL_REG &= ~GPT_ENAB; */
    MOV     a4, #0x0
    STR     a4, [a2, #0]
    
/*    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;*/
/*    ; Enable timer2, but do not use the prescaler (unit is 15 ns)*/
/*    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;*/
/*    ; GPTCntl->TIMER_2_CONTROL_REG  |=  GPT_ENAB | GPT_AUTO_RELOAD; */
    MOV     a4, #0x20
    STR     a4, [a2, #0]

/*    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
//    ; Wait until timer2 reaches 'val'
//    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
*/

    MOV     a3, #67
    MUL     a4, a1, a3   /*; Since 'val' is usec unit but timer2 unit is in 15 nsec, we*/
                     /*; need to multiply it by 67.*/

    MOV     a1, a4

    LDR     a3, =TIMER_COUNT2   /* ; keep the timer_count2 register address in a3*/

loop:
    LDR     a4, [a3, #0]
    CMP     a4, a1
    BLT     loop
    
/*    ; turn the timer off*/
/*    ; GPTCntl->TIMER_2_CONTROL_REG &= ~GPT_ENAB; */
    MOV     a4, #0x0
    STR     a4, [a2, #0]

/*    ;  return();*/
/*    ;*/
    MOV		pc, lr     /* ; Restore lr*/
      
/*;}*/

/*	END*/
.end