mpmc_pl175_ddr.s.svn-base

Spearhead2000 的 USB驱动程序

/*AREA PL175_INIT, CODE, READONLY*/


#define ApbBase  0x12000000

#define APB_DisableWriteProt	ApbBase + 0x20
#define APB_DisableReadProt	ApbBase + 0x40

/*ApbBase			EQU  0x12000000*/

/*APB_DisableWriteProt	EQU  ApbBase + 0x20*/
/*APB_DisableReadProt	EQU  ApbBase + 0x40*/

/*;  /*****************************************************************************
//;   *                                                                           *
//;   * Defines for ST SDRAM delay line.                                          *
//;   * The register are in apb_configuration                                     *   
//;   *                                                                           *
*/
/*;   ***************************************************************************** */

#define APBCfgBase  0x12003000
                                                                                                                             
#define SDRAM_CS0_MAX_ADDR APBCfgBase + 0x010  /*; // Base + 10*/
#define SDRAM_OUTPUT_CLOCK_DELAY APBCfgBase + 0x050 /* ; // Base + 50*/
#define SDRAM_INTPUT_CLOCK_DELAY APBCfgBase + 0x054 /* ; // Base + 54*/
#define SDRAM_FB_CLOCK_SOURCE APBCfgBase + 0x058  /*; // Base + 58*/
#define SDRAM_DQS_LO   APBCfgBase + 0x05C /* ; // Base + 5C*/
#define SDRAM_DQS_HI   APBCfgBase + 0x060 /* ; // Base + 60*/

/*APBCfgBase  	          EQU  0x12003000

//SDRAM_CS0_MAX_ADDR       EQU  APBCfgBase + 0x010  ; // Base + 10
//SDRAM_OUTPUT_CLOCK_DELAY EQU  APBCfgBase + 0x050  ; // Base + 50
//SDRAM_INTPUT_CLOCK_DELAY EQU  APBCfgBase + 0x054  ; // Base + 54
//SDRAM_FB_CLOCK_SOURCE    EQU  APBCfgBase + 0x058  ; // Base + 58
//SDRAM_DQS_LO             EQU  APBCfgBase + 0x05C  ; // Base + 5C
//SDRAM_DQS_HI             EQU  APBCfgBase + 0x060  ; // Base + 60

//;  *****************************************************************************
//;   *                                                                           *
//;   * Defines for MPMC PL175.                                                  *
//;   *                                                                           *
//;   *****************************************************************************
*/


#define MPMCBase  0x1000C000

#define MPMCControl MPMCBase + 0x000 /* ; Control register*/	   	       
#define MPMCStatus  MPMCBase + 0x004 /* ; Status register*/  	       
#define MPMCConfig  MPMCBase + 0x008 /* ; Configuration register */
#define MPMCDynamicControl MPMCBase + 0x020 /* ; Dynamic memory control register*/
#define MPMCDynamicRefresh MPMCBase + 0x024  /*; Dynamic memory refresh timer*/
#define MPMCDynamicReadConfig  MPMCBase + 0x028 /* ; Read Data Configuration Register*/
#define MPMCDynamictRP    MPMCBase + 0x030 /* ; Dynamic memory precharge command period (tRP)*/
#define MPMCDynamictRAS   MPMCBase + 0x034 /* ; Dynamic memory precharge period (tRAS)*/
#define MPMCDynamictSREX  MPMCBase + 0x038  /*; Dynamic memory self refresh exit time (tSREX)*/
#define MPMCDynamictWR MPMCBase + 0x044     /* ; Dynamic memory write recovery time (tWR)*/
#define MPMCDynamictRC MPMCBase + 0x048     /*; Dynamic memory auto refresh and active command period (tRC)*/
#define MPMCDynamictRFC MPMCBase + 0x04c  /*; Dynamic memory auto refresh period, and auto refresh to active command period (tRFC)*/
#define MPMCDynamictXSR  MPMCBase + 0x050  /* ; Dynamic memory exit self refresh to active command time (tXSR)*/
#define MPMCDynamictRRD  MPMCBase + 0x054  /*; Dynamic memory active bank A to active B time (tRRD)*/
#define MPMCDynamictMRD  MPMCBase + 0x058  /*; Dynamic memory load mode register to active command time (tMRD)*/
#define MPMCDynamictCDLR MPMCBase + 0x05c  /*; Dynamic memory write to read command time (tCDLR)*/

#define MPMCStaticExtendedWait MPMCBase + 0x080  /*; Static memory extended wait*/

/*; Dynamic memory bank registers  */
#define MPMCDynamicConfig0  MPMCBase + 0x100  /*; Dynamic memory configuration register*/
#define MPMCDynamicRasCas0  MPMCBase + 0x104  /*; Dynamic memory RAS and CAS delay*/
#define MPMCDynamicConfig1  MPMCBase + 0x120  /*; Dynamic memory configuration register*/
#define MPMCDynamicRasCas1  MPMCBase + 0x124  /*; Dynamic memory RAS and CAS delay*/
#define MPMCDynamicConfig2  MPMCBase + 0x140  /*; Dynamic memory configuration register*/
#define MPMCDynamicRasCas2  MPMCBase + 0x144  /*; Dynamic memory RAS and CAS delay*/
#define MPMCDynamicConfig3  MPMCBase + 0x160  /*; Dynamic memory configuration register*/
#define MPMCDynamicRasCas3  MPMCBase + 0x164  /*; Dynamic memory RAS and CAS delay*/
 
/*; Static memory bank registers  */
#define MPMCStaticConfig0   MPMCBase + 0x200  /*; Static memory configuration register*/
#define MPMCStaticWaitWen0  MPMCBase + 0x204  /*; Static memory write enable delay*/
#define MPMCStaticWaitOen0  MPMCBase + 0x208  /*; Static memory output enable delay*/
#define MPMCStaticWaitRd0   MPMCBase + 0x20c  /*; Static memory read delay*/
#define MPMCStaticWaitPage0 MPMCBase + 0x210  /*; Static memory page mode read delay*/
#define MPMCStaticWaitWr0   MPMCBase + 0x214  /*; Static memory write delay*/
#define MPMCStaticWaitTurn0 MPMCBase + 0x218  /*; Static memory turn round delay*/

#define MPMCStaticConfig1   MPMCBase + 0x220  /*; Static memory configuration register*/
#define MPMCStaticWaitWen1  MPMCBase + 0x224  /*; Static memory write enable delay*/
#define MPMCStaticWaitOen1  MPMCBase + 0x228  /*; Static memory output enable delay*/
#define MPMCStaticWaitRd1   MPMCBase + 0x22c  /*; Static memory read delay*/
#define MPMCStaticWaitPage1    MPMCBase + 0x230  /*; Static memory page mode read delay*/
#define MPMCStaticWaitWr1      MPMCBase + 0x234  /*; Static memory write delay*/
#define MPMCStaticWaitTurn1    MPMCBase + 0x238  /*; Static memory turn round delay*/

#define MPMCStaticConfig2      MPMCBase + 0x240  /*; Static memory configuration register*/
#define MPMCStaticWaitWen2     MPMCBase + 0x244  /*; Static memory write enable delay*/
#define MPMCStaticWaitOen2     MPMCBase + 0x248  /*; Static memory output enable delay*/
#define MPMCStaticWaitRd2      MPMCBase + 0x24c  /*; Static memory read delay*/
#define MPMCStaticWaitPage2    MPMCBase + 0x250  /*; Static memory page mode read delay*/
#define MPMCStaticWaitWr2      MPMCBase + 0x254  /*; Static memory write delay*/
#define MPMCStaticWaitTurn2    MPMCBase + 0x258  /*; Static memory turn round delay*/

#define MPMCStaticConfig3      MPMCBase + 0x260  /*; Static memory configuration register*/
#define MPMCStaticWaitWen3     MPMCBase + 0x264  /*; Static memory write enable delay*/
#define MPMCStaticWaitOen3     MPMCBase + 0x268  /*; Static memory output enable delay*/
#define MPMCStaticWaitRd3      MPMCBase + 0x26c  /*; Static memory read delay*/
#define MPMCStaticWaitPage3    MPMCBase + 0x270  /*; Static memory page mode read delay*/
#define MPMCStaticWaitWr3      MPMCBase + 0x274  /*; Static memory write delay*/
#define MPMCStaticWaitTurn3    MPMCBase + 0x278  /*; Static memory turn round delay*/

/*; AHB port registers  */
#define MPMCAHBControl0        MPMCBase + 0x400  /*; AHB control register */
#define MPMCAHBStatus0         MPMCBase + 0x404  /*; AHB status register  */
#define MPMCAHBTimeOut0        MPMCBase + 0x408  /*; AHB time out register*/	
    
#define MPMCAHBControl1        MPMCBase + 0x420  /*; AHB control register */
#define MPMCAHBStatus1         MPMCBase + 0x424  /*; AHB status register  */
#define MPMCAHBTimeOut1        MPMCBase + 0x428  /*; AHB time out register*/	
    
#define MPMCAHBControl2        MPMCBase + 0x440  /*; AHB control register */
#define MPMCAHBStatus2         MPMCBase + 0x444  /*; AHB status register  */	
#define MPMCAHBTimeOut2        MPMCBase + 0x448  /*; AHB time out register*/
    
#define MPMCAHBControl3        MPMCBase + 0x460  /*; AHB control register */	
#define MPMCAHBStatus3         MPMCBase + 0x464  /*; AHB status register  */
#define MPMCAHBTimeOut3        MPMCBase + 0x468  /*; AHB time out register*/	
    
#define MPMCAHBControl4        MPMCBase + 0x480  /*; AHB control register */
#define MPMCAHBStatus4         MPMCBase + 0x484  /*; AHB status register  */	
#define MPMCAHBTimeOut4        MPMCBase + 0x488  /*; AHB time out register*/
    
#define MPMCAHBControl5        MPMCBase + 0x4a0  /*; AHB control register */	
#define MPMCAHBStatus5         MPMCBase + 0x4a4  /*; AHB status register  */
#define MPMCAHBTimeOut5        MPMCBase + 0x4a8  /*; AHB time out register*/	
    
#define MPMCTestControl        MPMCBase + 0xf00  /*; Test control register*/

#define MPMCTestInput0         MPMCBase + 0xf20  /*; Test input register*/
#define MPMCTestInput1         MPMCBase + 0xf24  /*; Test input register*/

#define MPMCTestOutput         MPMCBase + 0xf40  /*; Test output register*/

#define MPMCPeriphID4          MPMCBase + 0xfd0  /*; Peripheral identification register bits [39:32]*/
#define MPMCPeriphID5          MPMCBase + 0xfd4  /*; Reserved for peripheral identification register*/
#define MPMCPeriphID6          MPMCBase + 0xfd8  /*; Reserved for peripheral identification register*/
#define MPMCPeriphID7          MPMCBase + 0xfdc  /*; Reserved for peripheral identification register*/
#define MPMCPeriphID0          MPMCBase + 0xfe0  /*; Peripheral identification register bits [7:0]*/
#define MPMCPeriphID1          MPMCBase + 0xfe4  /*; Peripheral identification register bits [15:8]*/
#define MPMCPeriphID2          MPMCBase + 0xfe8  /*; Peripheral identification register bits [23:16]*/
#define MPMCPeriphID3          MPMCBase + 0xfec  /*; Peripheral identification register bits [31:24]*/
#define MPMCCellID0            MPMCBase + 0xff0  /*; PrimeCell identification register bits [7:0]*/
#define MPMCCellID1            MPMCBase + 0xff4  /*; PrimeCell identification register bits [15:8]*/
#define MPMCCellID2            MPMCBase + 0xff8  /*; PrimeCell identification register bits [23:16]*/
#define MPMCCellID3            MPMCBase + 0xffc  /*; PrimeCell identification register bits [31:24]*/


/*;*
//; *   Company: Micron Technology, Inc.
//; *   Part Number: MT46V16M16 (4 Mb x 16 x 4 Banks)
//; *
//; *
*/


#define PL175_DYNAMIC_REFRESH_TIME_INIT   50   
#define PL175_DYNAMIC_REFRESH_TIME        (PL175_DYNAMIC_REFRESH_TIME_INIT + 5)

#define PL175_DYNAMIC_TRP_INIT            2
#define PL175_DYNAMIC_TRAS_INIT           5
#define PL175_DYNAMIC_TSREX_INIT          6
#define PL175_DYNAMIC_TWR_INIT            2
#define PL175_DYNAMIC_TRC_INIT            8
#define PL175_DYNAMIC_TRFC_INIT           8
#define PL175_DYNAMIC_TXSR_INIT           6
#define PL175_DYNAMIC_TRRD_INIT           2
#define PL175_DYNAMIC_TMRD_INIT           2
#define PL175_DYNAMIC_TCDLR_INIT          15
#define STATIC_EXTENDED_WAIT_INIT   	  50
#define STATIC_EXTENDED_WAIT        	  (STATIC_EXTENDED_WAIT_INIT + 5)

#define PL175_RAS_CAS_LATENCY             0x0282 /*; RAS LAT 2clk - CAS LAT 2.5clk*/


#define PAUSE_POWER_UP_INIT         	  100  /*; unit is  usec*/
#define PAUSE_MEM_INIT              	  200  /*; unit is  usec*/
#define PAUSE_REFRESH_INIT          	  40   /*; unit is  usec*/
/*;PAUSE_POWER_UP_INIT         	  EQU 0  ; TEST - do not wait*/
/*;PAUSE_MEM_INIT              	  EQU 0  ; TEST - do not wait*/
/*;PAUSE_REFRESH_INIT          	  EQU 0  ; TEST - do not wait*/

#define PL175_ENDIANITY                   0  /*; little endian*/
#define PL175_DATA_STRATEGY               0x0000  /*; SDR : (CLOCK_DELAYED + CAPTURE_NEGATIVE)*/
                                             /*; DDR : (CLOCK_DELAYED + CAPTURE_NEGATIVE)*/

#ifdef __SPEARHEAD_64MB
//;64 MB of SDRAM 
#define PL175_CONFIG                      0x884 //;DDR_SDRAM - NOT_WRITE_PROTECTED - 512MB_13_10_RBC_16BIT

#define uSDRAMModeConfig                  0x002c2000  /*; Mode reg is 0x61*/
#define uSDRAMExtModeConfig               0x00001000   
#define uDDRResetModeConfig               0x000C2000

#define SDRAM_BANK_SIZE			  0x04000000

#else //;__SPEARHEAD_64MB

//;32 MB of SDRAM
#define PL175_CONFIG                      0x684 //;DDR_SDRAM - NOT_WRITE_PROTECTED - 256MB_13_9_RBC_16BIT
                                                                                                                             
#define uSDRAMModeConfig                  0x00161000  /*; Mode reg is 0x61*/
#define uSDRAMExtModeConfig               0x00000400
#define uDDRResetModeConfig               0x00061000
                                                                                                                             
#define SDRAM_BANK_SIZE                   0x02000000
#endif //;__SPEARHEAD_64MB


/*EXPORT PL175_init_DDR*/

.global PL175_init_DDR
PL175_init_DDR:

/*;/*************************************************************************
//;/*                                                                       *
//;/* FUNCTION                                                              *
//;/*                                                                       *
//;/*      PL175_init_DDR                                                   *
//;/*                                                                       *
//;/* DESCRIPTION                                                           *
//;/*                                                                       *
//;/*      This routine initializes the DRAM Controller.                    *
//;/*                                                                       *
//;/* AUTHOR                                                                *
//;/*                                                                       *
//;/*      A. Visconti - ST Microelectronics                                *
//;/*                                                                       *
//;*************************************************************************
//;VOID  PL175_init_DDR(void)
//;{

//    ; This code can be optimized using multiple store...
*/
        
/*PL175_init_DDR ROUT*/