mmu946t.s.svn-base

Spearhead2000 的 USB驱动程序

;/*****************************************************************************
; * Copyright (c) ARM Limited 1998, 1999.  All rights reserved.
; ****************************************************************************/
;/*****************************************************************************
;
;   This file contains the COPROCESSOR access macros for the ARM946T processor
;
;   $Id: mmu946T.s,v 1.1 2005/05/26 15:51:47 sp_head Exp $
;   $Log: mmu946T.s,v $
;   Revision 1.1  2005/05/26 15:51:47  sp_head
;   user NI
;
;   Revision 1.1.1.2  2004/12/03 15:34:24  spear
;   First import from CRD
;
;   Revision 1.1.1.1  2004/12/02 11:07:22  spear
;   First import from CRD
;
;   
;    Revision: 1.1 Mon Sep 13 21:32:56 2004 gazzina
;    freeze pre-AFE
;   
;    Revision: 1.3 Tue Nov 11 11:53:28 2003 gazzina
;    adding some itcm macros  itcm
;   
;    Revision: 1.2 Tue Feb  4 10:11:44 2003 lert
;    In the midnight hour it's just time to add some nice macro to handle TCM....  Added some macros for TCM Handlers
; 
;*****************************************************************************/

        MACRO
        NO_CLEAR_WBUFFER        $state
        MEND
	
;Flag that this processor does not have an MMU
;
	MACRO
	CHECK_FOR_MMU_946T	$tmp
	BICS			$tmp, $tmp, $tmp	; Clear tmp & set Z (FALSE)
	MEND

;Flag that this processor has an MPU
;
	MACRO
	CHECK_FOR_MPU_946T	$tmp
	MOVS	$tmp, #1		; Set tmp & clear Z (TRUE)
	MEND

;Flag that this processor has a Cache
;
	MACRO
	CHECK_CACHE_946T	$tmp
	MOVS			$tmp, #1 ; Set tmp & clear Z (TRUE)
	MEND

;Flag that this processor does not have a unified cache
;
	MACRO
	CHECK_UNIFIED_946T	$tmp
	BICS	$tmp, $tmp, $tmp	; Clear tmp & set Z (FALSE)
	MEND

;Compare (uHAL supplied) processor ID with ARM 946
;
	MACRO
	CHECK_CPUID_946T	$id, $tmp
	RDCPU_ID_946T	$id, $tmp
	SUB	$tmp, $tmp, #0x900
	CMP	$tmp, #0x46		; set Z if it is an ARM 946
	MEND

;Compare (uHAL supplied) processor Vendor ID with 'A'RM.
;
	MACRO
	CHECK_VENDOR_946T	$id, $tmp
	RDCPU_VENDOR_946T	$id, $tmp
	CMP	$tmp, #0x41		; I'll have an 'A' please, Bob.
	MEND

;Default is this processor does not implement branch prediction
; 
        MACRO
        NO_CHECK_FOR_BRANCH_PRED        $tmp
        BICS    $tmp, $tmp, $tmp        ; Default - Clear tmp & set Z (FALSE)
        MEND

; ------------------------------------------------------------------
;Macros to hide internals of cache implementation on each processor
;
	MACRO
        CLEAR_IDC_946T	$state
        CLEAR_ICACHE_946T	$state
        CLEAR_DCACHE_946T	$state
	; No Write Buffer - Can't turn off on a 9x0
	MEND

	MACRO
        CLEAR_ICACHE_946T	$state
        BIC     $state, $state, #EnableIcache   ; No ICache
	MEND

	MACRO
        CLEAR_DCACHE_946T	$state
        BIC     $state, $state, #EnableDcache   ; No DCache
	MEND

        ; No Write Buffer enable on 946

	MACRO
	CLEAR_MMU_946T	$state
        BIC     $state, $state, #EnableMMU	; Disable MMU
	MEND


	MACRO
        SET_IDC_946T	$state
        SET_ICACHE_946T	$state
        SET_DCACHE_946T	$state
	; No Write Buffer - Can't turn on on a 946
	MEND

	MACRO
        SET_ICACHE_946T	$state
        ORR	$state, $state, #EnableIcache   ; Enable ICache
	MEND

	MACRO
        SET_DCACHE_946T	$state
        ORR	$state, $state, #EnableDcache   ; Enable DCache
	MEND

	; No Write Buffer - Can't turn on on a 946

	MACRO
	SET_MMU_946T	$state
        ORR	$state, $state, #EnableMMU	; Enable MMU
	MEND

	MACRO
	SET_BIGEND_946T	$state
        ORR	$state, $state, #EnableBigEndian	; Set BigEndian
	MEND

	MACRO
	TEST_MMU_946T	$tmp
	RDMMU_STATE_946T	$tmp
	AND	$tmp, $tmp, #EnableMMU
	TEQ	$tmp, #EnableMMU
	MEND

	MACRO
	TEST_BIGEND_946T	$tmp
	RDMMU_STATE_946T	$tmp
	AND	$tmp, $tmp, #EnableBigEndian
	TEQ	$tmp, #EnableBigEndian
	MEND

	MACRO
	TEST_HIGHVECTORS_946T	$tmp
	RDMMU_STATE_946T	$tmp
	AND	$tmp, $tmp, #EnableHighVectors
	TEQ	$tmp, #EnableHighVectors
	MEND

	MACRO
	SET_HIGHVECTORS_946T	$tmp
	RDMMU_STATE_946T	$tmp
	ORR			$tmp, $tmp, #EnableHighVectors
	WRMMU_STATE_946T	$tmp
	MEND

	MACRO
	CLEAR_HIGHVECTORS_946T	$tmp
	RDMMU_STATE_946T	$tmp
	BIC	$tmp, $tmp, #EnableHighVectors
	WRMMU_STATE_946T	$tmp
	MEND

;------------------------------------------------------------------
;Read CPU Code (ID, Vendor revision etc.) register 
;
	MACRO
	RDCPU_CODE_946T	$id
	MRC p15, 0, $id, c0, c0 ,0
	MEND

;Extract CPU ID from CPU Code register
;
	MACRO
	RDCPU_ID_946T	$id, $tmp
	MRC p15, 0, $id, c0, c0 ,0
	MOV	$tmp, $id, LSL #16	; Clear bits 16-31
	MOV	$tmp, $tmp, LSR #20	; Move bits 15-3 to 12-0
	MEND

;Extract CPU Vendor from CPU Code register
;
	MACRO
	RDCPU_VENDOR_946T	$id, $tmp
	MRC p15, 0, $id, c0, c0 ,0
	MOV	$tmp, $id, LSR #24	; Move bits 31-24 to 7-0
	MEND

;Coprocessor read of ID register (cache line sizes)
;
	MACRO
	RDCACHE_SIZES_946T $reg_number
	MRC p15, 0, $reg_number, c0, c0 ,1
	MEND

;Coprocessor read of Control register 
;
	MACRO
	RDMMU_STATE_946T $reg_number
	MRC p15, 0, $reg_number, c1, c0 ,0
	MEND

;Coprocessor write of Control register 
;
	MACRO 
	WRMMU_STATE_946T $reg_number
	MCR p15, 0, $reg_number, c1, c0 ,0
	MEND

;-----------------------------------------------------------
; MPU support macros:

;Coprocessor write of MPU cache bits 
;
	MACRO 
	WRMPU_CacheBits_946T	$reg_number
	MCR p15, 0, $reg_number, c2, c0, 0
	MCR p15, 0, $reg_number, c2, c0, 1
	MEND

;Coprocessor write of MPU buffer bits 
;
	MACRO 
	WRMPU_BufferBits_946T	$reg_number
	MCR p15, 0, $reg_number, c3, c0, 0
	MEND

;Coprocessor write of MPU access bits 
;
; Use standard instead of extended access permissions

	MACRO 
	WRMPU_AccessBits_946T	$reg_number
	MCR p15, 0, $reg_number, c5, c0, 0	
	MCR p15, 0, $reg_number, c5, c0, 1
	MEND

;Coprocessor write of MPU region registors 
;
	MACRO 
	WRMPU_Region_946T	$region, $reg_number
	MCR p15, 0, $reg_number, c6, c$region, 0
	MEND

;-----------------------------------------------------------
;Coprocessor cache control 
;Flush I & D Caches
;
	MACRO 
	WRCACHE_FlushIDC_946T $reg_number
	WRCACHE_FlushIC_946T $reg_number
	WRCACHE_FlushDC_946T $reg_number
	MEND

;Coprocessor cache control 
;Flush ICache
;
	MACRO 
	WRCACHE_FlushIC_946T $reg_number
	MCR p15,0,$reg_number,c7,c5,0
	MEND

;Coprocessor cache control 
;Flush DCache
;
	MACRO 
	WRCACHE_FlushDC_946T $reg_number
	MCR p15,0,$reg_number,c7,c6,0
	MEND

;Coprocessor cache control 
;Flush DCache entry
;
	MACRO 
	WRCACHE_CacheFlushDentry_946T $reg_number
	WRCACHE_FlushDC_946T $reg_number
	MEND

;Coprocessor cache control 
;Clean DCache entry
;
	MACRO 
	WRCACHE_CleanDCentry_946T $reg_number
	MCR p15, 0, $reg_number, c7, c10, 1
	MEND

;Coprocessor cache control 
;Clean + Flush DCache entry
;
	MACRO 
	WRCACHE_Clean_FlushDCentry_946T $reg_number
	MCR p15, 0, $reg_number, c7, c14, 1
	MEND

;Drain Write Buffer.
;
	MACRO
	WRCACHE_DrainWriteBuffer_946T $reg_number
	MCR p15,0,$reg_number,c7,c10,4
	MEND

;Flush TLB 
;
	MACRO
	WRMMU_FlushTB_946T $reg_number
	WRMMU_FlushITB_946T $reg_number
	WRMMU_FlushDTB_946T $reg_number
	MEND

;Flush Instruction TLB 
;
	MACRO
	WRMMU_FlushITB_946T $reg_number
	MCR p15,0,$reg_number,c8,c5,0
	MEND

;Flush Data TLB
;
	MACRO
	WRMMU_FlushDTB_946T $reg_number
	MCR p15,0,$reg_number,c8,c6,0
	MEND

;Coprocessor cache control 
;Clean DCache
;
	MACRO 
	WRCACHE_CleanDCache_946T	$w1, $w2, $w3, $w4, $w5, $w6
	RDCACHE_SIZES_946T		$w2		; Get cache information

	MOV	$w3, #0xf		; 4 bit mask
	AND	$w4, $w3, $w2, LSR #18	; Get Cache Size
	MOV	$w3, #7			; 3 bit mask
	AND	$w5, $w3, $w2, LSR #15	; Get Cache Associativity
	AND	$w6, $w3, $w2, LSR #12	; Get Base and Line Length
	MOVS	$w3, $w6, LSR #2	; Get Base (and set flags)
	AND	$w6, $w6, #3		; Get Line Length

	; Calculate LSB of Index field
	;
	; 32 - Cache Associativity - Base
	RSB	$w2, $w5, #32
	SUB	$w2, $w2, $w3

	; Calculate MSB of Segment field
	;
	; 8 + Cache Size - Cache Associativity
	ADD	$w3, $w4, #8
	SUB	$w3, $w3, $w5

	; Calculate LSB of Segment field
	;
	; Line Length + 3
	ADD	$w4, $w6, #3

	; Calculate max value for Index field
	RSB	$w5, $w2, #32
	MOV	$w6, #1
	MOV	$w5, $w6, LSL $w5
	SUBNE	$w5, $w5, $w5, LSR #2
	SUB	$w5, $w5, #1

	; Calculate max value for Segment field
	SUB	$w3, $w3, $w4
	ADD	$w3, $w3, #1
	MOV	$w3, $w6, LSL $w3
	SUB	$w3, $w3, #1

	; Now finally clean the cache
1	MOV	$w6, $w3
2	MOV	$w1, $w5, LSL $w2
	ORR	$w1, $w1, $w6, LSL $w4
	MCR	p15, 0, $w1, c7, c10, 2	; Clean Line by Index (Not Address)
	SUBS	$w6, $w6, #1
	BGE	%B2
	SUBS	$w5, $w5, #1
	BGE	%B1

	MEND

;Clean DCache (only) from address in $reg1 to (excl) addr in $reg2
;
	MACRO
	WRCACHE_CleanDrange_946T	$reg1, $reg2
1      
        WRCACHE_CleanDCentry_946T $reg1
        ADD     $reg1, $reg1, #32
        CMP     $reg1, $reg2
        BLT     %B1
	MEND

;------------------------------------------------------------------
;Coprocessor test/clock/idle control 
;Enable Clock Switching
;
	MACRO
	WRCLK_EnableClockSW_946T	$reg
	RDMMU_STATE_946T	$reg
	ORR	$reg, $reg, #0xC0000000
	WRMMU_STATE_946T	$reg
	MEND

;Coprocessor test/clock/idle control 
;Disable Clock Switching
;
	MACRO
	WRCLK_DisableClockSW_946T	$reg
	RDMMU_STATE_946T	$reg
	BIC	$reg, $reg, #0xC0000000
	WRMMU_STATE_946T	$reg
	MEND

;Coprocessor test/clock/idle control 
;Disable nMCLK output
;
	MACRO
	WRCLK_DisablenMCLK_946T	$reg
	MEND

;Coprocessor test/clock/idle control 
;Wait for Interrupt
;
	MACRO
	WRTEST_WaitInt_946T	$reg
	MCR p15, 0, $reg_number, c7, c0, 4
	MEND

;------------------------------------------------------------------
;       TCM MACROS
;------------------------------------------------------------------
	;; TCM PHysical Size
	MACRO
	GET_ITCM_PHY_SZ $reg
	MRC p15, 0, $reg, c0, c0, 2
	AND $reg, $reg, #0x000003C0 
	MOV $reg, $reg, LSR #6   ; bisogna shiftarlo a dx di sei bit
	MEND
	
	;; TCM Regions --------------------------------------------
	MACRO
	WR_ITCM_REGION_REGISTER   $reg
	MCR p15, 0, $reg, c9, c1, 1
	MEND

	MACRO
	WR_DTCM_REGION_REGISTER   $reg
	MCR p15, 0, $reg, c9, c1, 0
	MEND

	MACRO
	RD_ITCM_REGION_REGISTER   $reg
	MRC p15, 0, $reg, c9, c1, 1
	MEND

	MACRO
	RD_DTCM_REGION_REGISTER   $reg
	MRC p15, 0, $reg, c9, c1, 0
	MEND
	
	;; Load Mode Handlers -------------------------------------
	MACRO
	SET_ITCM_LOAD_MODE        $reg
	MRC p15, 0, $reg, c1, c0, 0
	ORR $reg, $reg, #0x00080000
	MCR p15, 0, $reg, c1, c0, 0
	MEND

	MACRO
	SET_DTCM_LOAD_MODE        $reg
	MRC p15, 0, $reg, c1, c0, 0
	ORR $reg, $reg, #0x00020000
	MCR p15, 0, $reg, c1, c0, 0
	MEND

	MACRO
	RESET_ITCM_LOAD_MODE     $reg
	MRC p15, 0, $reg, c1, c0, 0
	BIC $reg, $reg, #0x00080000
	MCR p15, 0, $reg, c1, c0, 0
	MEND

	MACRO
	RESET_DTCM_LOAD_MODE     $reg
	MRC p15, 0, $reg, c1, c0, 0
	BIC $reg, $reg, #0x00020000
	MCR p15, 0, $reg, c1, c0, 0
	MEND

	;; Enable/Disable TCM -------------------------------------
	MACRO
	ENABLE_ITCM              $reg
	MRC p15, 0, $reg, c1, c0, 0
	ORR $reg, $reg, #0x00040000
	MCR p15, 0, $reg, c1, c0, 0
	MEND

	MACRO
	ENABLE_DTCM              $reg
	MRC p15, 0, $reg, c1, c0, 0
	ORR $reg, $reg, #0x00010000
	MCR p15, 0, $reg, c1, c0, 0
	MEND

	MACRO
	DISABLE_ITCM             $reg
	MRC p15, 0, $reg, c1, c0, 0
	BIC $reg, $reg, #0x00040000
	MCR p15, 0, $reg, c1, c0, 0
	MEND

	MACRO
	DISABLE_DTCM             $reg
	MRC p15, 0, $reg, c1, c0, 0
	BIC $reg, $reg, #0x00010000
	MCR p15, 0, $reg, c1, c0, 0
	MEND
	
;------------------------------------------------------------------
; MPU setup macro
;

	MACRO
	SET_MPU_REGION_946T	$num, $address, $size, $access

	;
	; Check that the address is correctly aligned, it must be
	; a multiple of size.
	;
	ASSERT (($address :AND: ((1 :SHL: ($size + 1)) - 1)) = 0)

MPU_REGION_$num	SETA (($address :AND: 0xFFFFF000) + ($size :SHL: 1) + 1)
MPU_CACHE	SETA MPU_CACHE :OR: ((($access :SHR: 3) :AND: 1) :SHL: $num)
MPU_BUFFER	SETA MPU_BUFFER :OR: ((($access :SHR: 2) :AND: 1) :SHL: $num)
MPU_ACCESS	SETA MPU_ACCESS :OR: ((($access :SHR: 10) :AND: 3) :SHL: ($num * 2))

	MEND

	END