📄 i2c.h.svn-base
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/*****************************************************************************//* This confidential and proprietary software may be used only as authorized *//* by a licensing agreement from STMicroelectronics. *//* In the event of publication, the following notice is applicable: *//* *//* (C) COPYRIGHT 2002 STMicroelectronics *//* Innovative Systems Design Group - Central R&D *//* ALL RIGHTS RESERVED *//* *//* The entire notice above must be reproduced on all authorized copies. *//* *//* -- File: i2c.h *//* -- Author: Nicola Imperato *//* -- Description: Header I2C *//* *//* -- Modification History: - 1.0 (8/4/2005) *//*****************************************************************************/#ifndef __I2C_H#define __I2C_Hextern void i2cInterrupt(unsigned int vector);extern void i2cInit(void);extern void i2cTest(void);void i2c_rx (char *buff_addr, char mem_addr, char nb , char slave_addr);#define APB_I2C_BASE 0x12007000typedef struct I2CController{ unsigned int CR; unsigned int SR1; unsigned int SR2; unsigned int CCR; unsigned int OAR1; unsigned int OAR2; unsigned int DR; } I2CController;#define I2CCntl ((volatile struct I2CController*) (APB_I2C_BASE))// Control Register bits#define CR_PE 0x0020 // Peripherial enable #define CR_ENGC 0x0010 // Enable general call // kept reserved as in the recent I2C doc#define CR_START 0x0008 // Start generation#define CR_ACK 0x0004 // Acknowledge enable#define CR_STOP 0x0002 // Stop generation#define CR_ITE 0x0001 // Interrupt enable// Status Register 1 bits#define SR1_EVF 0x0080 // Event flag#define SR1_TRA 0x0020 // Transmitter/Receiver #define SR1_BUSY 0x0010 // Bus Busy #define SR1_BTF 0x0008 // Byte transfer finished#define SR1_ADSL 0x0004 // Address matched (only in slave mode)#define SR1_MSL 0x0002 // Master/Slave#define SR1_SB 0x0001 // Start bit (only in master mode)#endif //__I2C_H
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