📄 gdma.h.svn-base
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///////////////////////////////////////////////////////////////////////////////// // Copyright (c) 2000 STMicroelectronics // All Rights Reserved // // PROJECT SPEARHEAD///////////////////////////////////////////////////////////////////////////////////*****************************************************************************//** **//** Copyright (c) 2000 ST Microelectronics **//** All rights reserved **//** **//** Filename : dma.equ **//** Author : Armando Visconti **//** Revision : 1.0 **//** **//** **//** **//*****************************************************************************/*****************************************************************************//* This confidential and proprietary software may be used only as authorized *//* by a licensing agreement from STMicroelectronics. *//* In the event of publication, the following notice is applicable: *//* *//* (C) COPYRIGHT 2002 STMicroelectronics *//* Innovative Systems Design Group - Central R&D *//* ALL RIGHTS RESERVED *//* *//* The entire notice above must be reproduced on all authorized copies. *//* *//* -- File: dma.h *//* -- Author: Francesco Lertora <francesco.lertora@st.com> *//* -- Description: Header of DMA Driver *//* *//* -- Modification History: - 1.1 (04/11/2002) *//*****************************************************************************/// $Id: gdma.h,v 1.1.1.1 2004/06/03 10:44:46 visconti Exp $// $Log: gdma.h,v $// Revision 1.1.1.1 2004/06/03 10:44:46 visconti////// // Revision: 1.2 Thu Nov 28 16:59:07 2002 lert// Remove the DMA_TEST_2 label....conflict...// // Revision: 1.1 Mon Nov 4 18:05:22 2002 lert// First Version/*#define APB_DMABase 0x1200C000 base address for gDMA1*/#define APB_DMABase 0x1200D000 /*base address for gDMA2*//***************************************************************************** * Defines for DMA Controller * *****************************************************************************/// DMA CTRL register values #define DMA_Enab 0x0001 // DMA Enable bit#define DMA_FixSrc 0x0000 // Source Address is fixed (FIFO)#define DMA_IncSrc 0x0002 // Source Address is incrememnted after transfer#define DMA_DecSrc 0x0004 // Source Address is decrememnted after transfer#define DMA_FixDst 0x0000 // Destination Address is fixed (FIFO)#define DMA_IncDst 0x0008 // Destination Address is incrememnted after transfer#define DMA_DecDst 0x0010 // Destination Address is decrememnted after transfer#define DMA_SrcSzB 0x0000 // Source Data size (1 byte)#define DMA_SrcSzH 0x0020 // Source Data size (1 Halword)#define DMA_SrcSzW 0x0040 // Source Data size (1 Word)#define DMA_SrcBst1 0x0000 // Source Data burst (1 beat)#define DMA_SrcBst4 0x0080 // Source Data burst (4 beat)#define DMA_SrcBst8 0x0100 // Source Data burst (8 beat)#define DMA_SrcBst16 0x0180 // Source Data burst (16 beat)#define DMA_DstSzB 0x0000 // Destination Data size (1 byte)#define DMA_DstSzH 0x0200 // Destination Data size (1 Halword)#define DMA_DstSzW 0x0400 // Destination Data size (1 Word)#define DMA_Mem2Mem 0x0800 // Memory to Memory transfer request bit#define DMA_Dir 0x2000 // Transfer Direction request bit// DMA Mask/Clear/Status Registers values#define DMA_S0Irq 0x0001 // DMA Stream 0 IRQ#define DMA_S1Irq 0x0002 // DMA Stream 1 IRQ#define DMA_S2Irq 0x0004 // DMA Stream 2 IRQ#define DMA_S3Irq 0x0008 // DMA Stream 3 IRQ#define DMA_CH0 0x00000000 // DMA channel 0#define DMA_CH1 0x00000001 // DMA channel 1#define DMA_CH2 0x00000002 // DMA channel 2#define DMA_CH3 0x00000003 // DMA channel 3typedef struct DMA_Control_Struct{ unsigned int DMASource_Lo_0; unsigned int DMASource_Hi_0; unsigned int DMADestLo_0; unsigned int DMADestHi_0; unsigned int DMAMax_0; unsigned int DMACtrl_0; unsigned int DMASoCurrLo_0; unsigned int DMASoCurrHi_0; unsigned int DMADeCurrLo_0; unsigned int DMADeCurrHi_0; unsigned int DMATCnt_0; unsigned char __fill_0[20]; unsigned int DMASource_Lo_1; unsigned int DMASource_Hi_1; unsigned int DMADestLo_1; unsigned int DMADestHi_1; unsigned int DMAMax_1; unsigned int DMACtrl_1; unsigned int DMASoCurrLo_1; unsigned int DMASoCurrHi_1; unsigned int DMADeCurrLo_1; unsigned int DMADeCurrHi_1; unsigned int DMATCnt_1; unsigned char __fill_1[20]; unsigned int DMASource_Lo_2; unsigned int DMASource_Hi_2; unsigned int DMADestLo_2; unsigned int DMADestHi_2; unsigned int DMAMax_2; unsigned int DMACtrl_2; unsigned int DMASoCurrLo_2; unsigned int DMASoCurrHi_2; unsigned int DMADeCurrLo_2; unsigned int DMADeCurrHi_2; unsigned int DMATCnt_2; unsigned char __fill_2[20]; unsigned int DMASource_Lo_3; unsigned int DMASource_Hi_3; unsigned int DMADestLo_3; unsigned int DMADestHi_3; unsigned int DMAMax_3; unsigned int DMACtrl_3; unsigned int DMASoCurrLo_3; unsigned int DMASoCurrHi_3; unsigned int DMADeCurrLo_3; unsigned int DMADeCurrHi_3; unsigned int DMATCnt_3; unsigned char __fill_3[4]; unsigned int DMAMask; unsigned int DMAClr; unsigned int DMAStatus;} DMA_Control_Struct;#define DMACtrl ((volatile struct DMA_Control_Struct*)(APB_DMABase))
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