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/******************************************************************************* ** ** ** Copyright (c) 1999 ST Microelectronics ** ** All rights reserved ** ** ** ** Filename : PNCU_DMAMAC.h ** ** Author : Armando Visconti ** ** Revision : 1.0 ** ** ** ** ** ** ** *******************************************************************************/#ifndef __PNCU_DMAMAC_HEADER#define __PNCU_DMAMAC_HEADER//#define NO_CACHE//typedef unsigned long size_t;#ifdef NO_CACHE#define MAC_ALIAS_MEMORY 0x00020000 /* space left for code and stacks */#else#define MAC_ALIAS_MEMORY 0x80000000#endif/***************************************************************************** * Defines for ITC *****************************************************************************///#define ITC_Base 0x30000000 /***************************************************************************** * Defines for PNCU DMA_MAC *****************************************************************************//* DMA_MAC Descriptor definition*/typedef struct { int DmaMac_Cntl; char *DmaMac_Addr; int DmaMac_Next; int TxRx_Status; } DmaMacDescr;#define RX_MAC_DescrTable_RAM 0x60400 // 0x21000400#define TX_MAC_DescrTable_RAM 0x60000 // 0x21000000 #define RX_MAC_DESCR_NUM 16#define TX_MAC_DESCR_NUM 16#define MAC_MAX_FRAME_SZ 1520#define MAC_TRIGGER 8#define MAC_END_TEST 50/* DEFINE OF MAC_TEST_DESCR_NUM FOR ALL TEST */#ifdef _MAC_BROADCAST_DISABLE #define MAC_TEST_DESCR_NUM 3#else #define MAC_TEST_DESCR_NUM 7#endif// DMA_MAC Base Address#define DmaMac_Base 0x14000000 // I/O Base Address of DMA_MAC /***************************************************************************** * DMA_MAC Registers *****************************************************************************//* DMA_MAC Status & Control Register Addresses*/#define DmaMac_Stat ((volatile unsigned int *) (DmaMac_Base + 0x000))#define DmaMac_Stat_Msk 0xffffff08#define DmaMac_Stat_Rst 0x4a4a0100 /* ... Values */#define DmaMac_SRst 0x00000001#define DmaMac_Loopb 0x00000002#define DmaMac_BigEndian 0x00000004#define DmaMac_RXBurst_16 0x00000000#define DmaMac_RXBurst_08 0x00000010#define DmaMac_RXBurst_04 0x00000020#define DmaMac_RXBurst_01 0x00000030#define DmaMac_TXBurst_16 0x00000000#define DmaMac_TXBurst_08 0x00000040#define DmaMac_TXBurst_04 0x00000080#define DmaMac_TXBurst_01 0x000000C0#define DmaMac_RevMsk 0x0000ff00#define DmaMac_RevU 0x00000100#define DmaMac_RxChStMsk 0x00030000 // RX_CHAN_STATUS#define DmaMac_RxChSt_no 0x00000000#define DmaMac_RxChSt_le 0x00010000#define DmaMac_RxChSt_he 0x00020000#define DmaMac_RxDataWMsk 0x000C0000 // RX_IO_DATA_WIDTH#define DmaMac_RxDataW_8 0x00000000 #define DmaMac_RxDataW_16 0x00040000 #define DmaMac_RxDataW_32 0x00080000 #define DmaMac_RxFifoSzMsk 0x00F00000 // RX_FIFO_SIZE#define DmaMac_RxFifoSz_2 0x00100000 #define DmaMac_RxFifoSz_4 0x00200000 #define DmaMac_RxFifoSz_8 0x00300000 #define DmaMac_RxFifoSz_16 0x00400000 #define DmaMac_RxFifoSz_32 0x00500000 #define DmaMac_TxChStMsk 0x03000000 // TX_CHAN_STATUS#define DmaMac_TxChSt_no 0x00000000#define DmaMac_TxChSt_le 0x01000000#define DmaMac_TxChSt_he 0x02000000#define DmaMac_TxDataWMsk 0x0C000000 // TX_IO_DATA_WIDTH#define DmaMac_TxDataW_8 0x00000000 #define DmaMac_TxDataW_16 0x04000000 #define DmaMac_TxDataW_32 0x08000000 #define DmaMac_TxFifoSzMsk 0xF0000000 // TX_FIFO_SIZE#define DmaMac_TxFifoSz_2 0x10000000 #define DmaMac_TxFifoSz_4 0x20000000 #define DmaMac_TxFifoSz_8 0x30000000 #define DmaMac_TxFifoSz_16 0x40000000 #define DmaMac_TxFifoSz_32 0x50000000 /* DMA_MAC Interrupt Sources Enable Register Addresses* * DMA_MAC Interrupt Sources Status Register Addresses*/#define DmaMac_IntEn ((volatile unsigned int *) (DmaMac_Base + 0x004))#define DmaMac_IntEn_Msk 0x92ef82ef#define DmaMac_IntEn_Rst 0x00000000#define DmaMac_IntStat ((volatile unsigned int *) (DmaMac_Base + 0x008))#define DmaMac_IntStat_Msk 0x92ef82ef#define DmaMac_IntStat_Rst 0x00050001 /* ... Values */#define DmaMac_RxEmpty 0x00000001#define DmaMac_RxFull 0x00000002#define DmaMac_RxEntry 0x00000004#define DmaMac_RxTo 0x00000008//#define DmaMac_RxRty 0x00000010#define DmaMac_PckLost 0x00000020#define DmaMac_RxNext 0x00000040#define DmaMac_RxDone 0x00000080//#define DmaMac_RxSErr 0x00000100#define DmaMac_RxMErr 0x00000200#define DmaMac_RxCurrDone 0x00008000#define DmaMac_TxEmpty 0x00010000#define DmaMac_TxFull 0x00020000#define DmaMac_TxEntry 0x00040000#define DmaMac_TxTo 0x00080000//#define DmaMac_TxRty 0x00100000#define DmaMac_TxIOReq 0x00200000#define DmaMac_TxNext 0x00400000#define DmaMac_TxDone 0x00800000//#define DmaMac_TxSErr 0x01000000#define DmaMac_TxMErr 0x02000000#define DmaMac_MACInt 0x10000000#define DmaMac_TxCurrDone 0x80000000/* DMA_MAC TX/RX DMA Start Register Addresses*/#define DmaMac_RxDMAStart ((volatile unsigned int *) (DmaMac_Base + 0x010))#define DmaMac_RxDMAStart_Msk 0x00ffffe5#define DmaMac_RxDMAStart_Rst 0x00000000#define DmaMac_TxDMAStart ((volatile unsigned int *) (DmaMac_Base + 0x030))#define DmaMac_TxDMAStart_Msk 0x00ffffe5#define DmaMac_TxDMAStart_Rst 0x00000000 /* ... Values */#define DmaMac_DMAEn 0x00000001//#define DmaMac_IOEn 0x00000002#define DmaMac_StartFetch 0x00000004#define DmaMac_TxPADDis 0x00000040 // TX only#define DmaMac_TxAddCRCDis 0x00000080 // TX only#define DmaMac_RxFilterFail 0x00000020 // RX only#define DmaMac_RxRuntFrame 0x00000040 // RX only#define DmaMac_RxCollSeen 0x00000080 // RX only#define DmaMac_DFetchDlyMsk 0x00FFFF00#define DmaMac_DFetchDlyU 0x00000100/* DMA_MAC TX/RX DMA Cntl Register Addresses*/#define DmaMac_RxDMACntl ((volatile unsigned int *) (DmaMac_Base + 0x014))#define DmaMac_RxDMACntl_Msk 0xffffdfff#define DmaMac_RxDMACntl_Rst 0x00000000#define DmaMac_TxDMACntl ((volatile unsigned int *) (DmaMac_Base + 0x034))#define DmaMac_TxDMACntl_Msk 0xffffdfff#define DmaMac_TxDMACntl_Rst 0x00000000 /* ... Values */#define DmaMac_XferCntMsk 0x00000FFF#define DmaMac_XferCntU 0x00000001#define DmaMac_ContEn 0x00001000#define DmaMac_NxtEn 0x00004000#define DmaMac_DlyEn 0x00008000#define DmaMac_Valid 0x00010000#define DmaMac_EntryTrigMsk 0x003E0000#define DmaMac_EntryTrigU 0x00020000#define DmaMac_AddrWrapMsk 0xFFC00000#define DmaMac_AddrWrapU 0x00400000/* DMA_MAC TX/RX DMA Addr Register Addresses*/#define DmaMac_RxDMAAddr ((volatile unsigned int *) (DmaMac_Base + 0x018))#define DmaMac_RxDMAAddr_Msk 0xffffffff#define DmaMac_TxDMAAddr ((volatile unsigned int *) (DmaMac_Base + 0x038))#define DmaMac_TxDMAAddr_Msk 0xffffffff /* ... Values */#define DmaMac_WrapEn 0x00000001#define DmaMac_FixAddr 0x00000002#define DmaMac_DMAAddrMsk 0xFFFFFFFC#define DmaMac_DMAAddrU 0x00000004/* DMA_MAC TX/RX DMA Next Register Addresses*/#define DmaMac_RxDMANext ((volatile unsigned int *) (DmaMac_Base + 0x01C))#define DmaMac_RxDMANext_Msk 0xffffffff#define DmaMac_TxDMANext ((volatile unsigned int *) (DmaMac_Base + 0x03C))#define DmaMac_TxDMANext_Msk 0xffffffff /* ... Values */#define DmaMac_NpolEn 0x00000001#define DmaMac_DescrAddrMsk 0xFFFFFFFC#define DmaMac_DescrAddrU 0x00000004/* DMA_MAC TX/RX DMA Current Address Register Addresses*/#define DmaMac_RxDMACAddr ((volatile unsigned int *) (DmaMac_Base + 0x020))#define DmaMac_RxDMACAddr_Msk 0xffffffff#define DmaMac_TxDMACAddr ((volatile unsigned int *) (DmaMac_Base + 0x040))#define DmaMac_TxDMACAddr_Msk 0xffffffff /* ... Values */#define DmaMac_CAddrMsk 0xFFFFFFFF#define DmaMac_CAddrU 0x00000001/* DMA_MAC TX/RX DMA Current XferCount Register Addresses*/#define DmaMac_RxDMACurrXCnt ((volatile unsigned int *) (DmaMac_Base + 0x024))#define DmaMac_RxDMACurrXCnt_Msk 0x00000fff#define DmaMac_TxDMACurrXCnt ((volatile unsigned int *) (DmaMac_Base + 0x044))#define DmaMac_TxDMACurrXCnt_Msk 0x00000fff /* ... Values */#define DmaMac_CurrXCntMsk 0x00000FFF#define DmaMac_CurrXCntU 0x00000001/* DMA_MAC TX/RX DMA FIFO Timeout Register Addresses*/#define DmaMac_RxDMAFifoTmOut ((volatile unsigned int *) (DmaMac_Base + 0x028))#define DmaMac_RxDMAFifoTmOut_Msk 0x0000ffff#define DmaMac_RxDMAFifoTmOut_Rst 0x00000000#define DmaMac_TxDMAFifoTmOut ((volatile unsigned int *) (DmaMac_Base + 0x048))#define DmaMac_TxDMAFifoTmOut_Msk 0x0000ffff#define DmaMac_TxDMAFifoTmOut_Rst 0x00000000 /* ... Values */#define DmaMac_FifoTmOutMsk 0x0000FFFF#define DmaMac_FifoTmOutU 0x00000001/* DMA_MAC TX/RX DMA FIFO Status Register Addresses*/#define DmaMac_RxDMAFifoStat ((volatile unsigned int *) (DmaMac_Base + 0x02C))#define DmaMac_RxDMAFifoStat_Msk 0x3f1f1f0f#define DmaMac_RxDMAFifoStat_Rst 0x00000001#define DmaMac_TxDMAFifoStat ((volatile unsigned int *) (DmaMac_Base + 0x04C))#define DmaMac_TxDMAFifoStat_Msk 0x3f1f1f0f#define DmaMac_TxDMAFifoStat_Rst 0x10000005 /* ... Values */#define DmaMac_FifoEmpty 0x00000001#define DmaMac_FifoFull 0x00000002#define DmaMac_FifoEntryT 0x00000004#define DmaMac_FifoDelayT 0x00000008#define DmaMac_FifoIOPMsk 0x00001F00#define DmaMac_FifoIOPU 0x00000100#define DmaMac_FifoDMAPMsk 0x001F0000#define DmaMac_FifoDMAPU 0x00010000#define DmaMac_FifoEntMsk 0x3F000000#define DmaMac_FifoEntU 0x01000000/***************************************************************************** * Ethernet IEEE802.3 definitions *****************************************************************************//* MAC Frame Format*/typedef struct { char MAC_DstAddr[6]; char MAC_SrcAddr[6];
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