uhc_ahb.h.svn-base

Spearhead2000 的 USB驱动程序

/******************************************************************************
**                                                                           **
**  Copyright (c) 2002 ST Microelectronics                                   **
**  All rights reserved                                                      **
**                                                                           **
**      Filename  :  uhc_ahb.h                                               **
**      Author    :  Stefano Romano                                          **
**      Revision  :  2.0                                                     **
**                                                                           **
**                                                                           **
**                                                                           **
******************************************************************************/
#ifdef     __cplusplus
extern  "C" {           /* C declarations in C++     */
#endif

#define VUINTP  volatile unsigned int *

/*****************************************************************************
 * USB2.0 Host Registers
 *****************************************************************************/
#define EHCI_Base0     0x10009000         // I/O Base Address of USB Host Controller
#define EHCI_Base1     0x1000D000         // I/O Base Address of USB Host Controller

/******************** Structure for I/O interface registers ********************/
typedef struct UHOSTController
{
  unsigned int  ehci_USBBASE;
  unsigned char Reserved_0[252];
  unsigned int  ehci_HCCAPBASE;            /*  EHCI USBBASE Register */
  unsigned int  ehci_HCSPARAMS;            /*  EHCI HCSPARAMS Register */
  unsigned int  ehci_HCCPARAMS;            /*  EHCI HCCPARAMS Register */
  unsigned char Reserved_1[4];
  unsigned int  ehci_USBCMD;               /*  USB Command Register */ 
  unsigned int  ehci_USBSTS;               /*  USB Status Register */ 
  unsigned int  ehci_USBINTR;              /*  USB Interrupt Register */ 
  unsigned int  ehci_FRINDEX;              /*  USB Frame Index Register */ 
  unsigned int  ehci_CTRLDSSEGMENT;        /*  USB 4G Segment Selector Register */ 
  unsigned int  ehci_PERIODICLISTBASE;     /*  USB Frame List Base Addr Register */ 
  unsigned int  ehci_ASYNLISTADDR;         /*  USB Next Async List Addr Register */ 
  unsigned char Reserved_2[34];
  unsigned int  ehci_CONFIGFLAG;           /*  USB Configured Flag Register */ 
  unsigned int  ehci_PORTSC_0;             /*  USB Port 0 Status/Control Register */ 
  unsigned int  ehci_PORTSC_1;             /*  USB Port 1 Status/Control Register */ 
  unsigned char Reserved_3[50];
  unsigned int  ehci_INSREG00;             /*  USB Synopsys Specific Register Frame Lengt for Sims*/ 
  unsigned int  ehci_INSREG01;             /*  USB Synopsys Specific Register */ 
  unsigned int  ehci_INSREG02;             /*  USB Synopsys Specific Register */ 
  unsigned int  ehci_INSREG03;             /*  USB Synopsys Specific Register */ 
  unsigned int  ehci_INSREG04;             /*  USB Synopsys Specific Register Debug Only*/ 
  unsigned int  ehci_INSREG05;             /*  USB Synopsys Specific Register */ 
} UHOSTController;

extern volatile struct UHOSTController *UHOSTCntl;
//#define UHOSTCntl ((volatile struct UHOSTController*) (EHCI_Base))
/*******************************************************************************/

/******************** Defines for registers fields ********************/
/* define for ehci_HCCPARAMS */
#define  EHCI_HCC_EECP(x)    (((x) >> 8) & 0xff) /* extended ports caps */
#define  EHCI_HCC_IST(x)     (((x) >> 4) & 0xf) /* isoc sched threshold */
#define  EHCI_HCC_ASPC(x)    ((x) & 0x4) /* async sched park cap */
#define  EHCI_HCC_PFLF(x)    ((x) & 0x2) /* prog frame list flag */
#define  EHCI_HCC_64BIT(x)   ((x) & 0x1) /* 64 bit address cap */

/* define for ehci_HCSPARAMS */
#define  EHCI_HCS_DEBUGPORT(x)       (((x) >> 20) & 0xf)
#define  EHCI_HCS_P_INDICATOR(x) ((x) & 0x10000)
#define  EHCI_HCS_N_CC(x)    (((x) >> 12) & 0xf) /* # of companion ctlrs */
#define  EHCI_HCS_N_PCC(x)   (((x) >> 8) & 0xf) /* # of ports per comp. */
#define  EHCI_HCS_PPC(x)     ((x) & 0x10) /* port power control */
#define  EHCI_HCS_N_PORTS(x) ((x) & 0xf) /* # of ports */

/* define for ehci_USBCMD */
#define  EHCI_CMD_ITC_M		0x00ff0000 /* RW interrupt threshold ctrl */
#define   EHCI_CMD_ITC_1	0x00010000
#define   EHCI_CMD_ITC_2	0x00020000
#define   EHCI_CMD_ITC_4	0x00040000
#define   EHCI_CMD_ITC_8	0x00080000
#define   EHCI_CMD_ITC_16	0x00100000
#define   EHCI_CMD_ITC_32	0x00200000
#define   EHCI_CMD_ITC_64	0x00400000
#define  EHCI_CMD_ASPME		0x00000800 /* RW/RO async park enable */
#define  EHCI_CMD_ASPMC		0x00000300 /* RW/RO async park count */
#define  EHCI_CMD_LHCR		0x00000080 /* RW light host ctrl reset */
#define  EHCI_CMD_IAAD		0x00000040 /* RW intr on async adv door bell */
#define  EHCI_CMD_ASE		0x00000020 /* RW async sched enable */
#define  EHCI_CMD_PSE		0x00000010 /* RW periodic sched enable */
#define  EHCI_CMD_FLS_M		0x0000000c /* RW/RO frame list size */
#define  EHCI_CMD_FLS(x)	(((x) >> 2) & 3) /* RW/RO frame list size */
#define  EHCI_CMD_HCRESET	0x00000002 /* RW reset */
#define  EHCI_CMD_RS		0x00000001 /* RW run/stop */

/* define for ehci_USBSTS */
#define  EHCI_STS_ASS		0x00008000 /* RO async sched status */
#define  EHCI_STS_PSS		0x00004000 /* RO periodic sched status */
#define  EHCI_STS_REC		0x00002000 /* RO reclamation */
#define  EHCI_STS_HCH		0x00001000 /* RO host controller halted */
#define  EHCI_STS_IAA		0x00000020 /* RWC interrupt on async adv */
#define  EHCI_STS_HSE		0x00000010 /* RWC host system error */
#define  EHCI_STS_FLR		0x00000008 /* RWC frame list rollover */
#define  EHCI_STS_PCD		0x00000004 /* RWC port change detect */
#define  EHCI_STS_ERRINT	0x00000002 /* RWC error interrupt */
#define  EHCI_STS_INT		0x00000001 /* RWC interrupt */
#define  EHCI_STS_INTRS(x)	((x) & 0x3f)

/* define for ehci_USBINTR */
#define EHCI_INTR_IAAE		0x00000020 /* interrupt on async advance ena */
#define EHCI_INTR_HSEE		0x00000010 /* host system error ena */
#define EHCI_INTR_FLRE		0x00000008 /* frame list rollover ena */
#define EHCI_INTR_PCIE		0x00000004 /* port change ena */
#define EHCI_INTR_UEIE		0x00000002 /* USB error intr ena */
#define EHCI_INTR_UIE		0x00000001 /* USB intr ena */

/* define for ehci_CONFIGFLAG */
#define  EHCI_CONF_CF		0x00000001 /* RW configure flag */

/* define for ehci_PORTSC */
#define  EHCI_PS_WKOC_E		0x00400000 /* RW wake on over current ena */
#define  EHCI_PS_WKDSCNNT_E	0x00200000 /* RW wake on disconnect ena */
#define  EHCI_PS_WKCNNT_E	0x00100000 /* RW wake on connect ena */
#define  EHCI_PS_PTC		0x000f0000 /* RW port test control */
#define  EHCI_PS_PIC		0x0000c000 /* RW port indicator control */
#define  EHCI_PS_PO		0x00002000 /* RW port owner */
#define  EHCI_PS_PP		0x00001000 /* RW,RO port power */
#define  EHCI_PS_LS		0x00000c00 /* RO line status */
#define  EHCI_PS_IS_LOWSPEED(x)	(((x) & EHCI_PS_LS) == 0x00000400)
#define  EHCI_PS_PR		0x00000100 /* RW port reset */
#define  EHCI_PS_SUSP		0x00000080 /* RW suspend */
#define  EHCI_PS_FPR		0x00000040 /* RW force port resume */
#define  EHCI_PS_OCC		0x00000020 /* RWC over current change */
#define  EHCI_PS_OCA		0x00000010 /* RO over current active */
#define  EHCI_PS_PEC		0x00000008 /* RWC port enable change */
#define  EHCI_PS_PE		0x00000004 /* RW port enable */
#define  EHCI_PS_CSC		0x00000002 /* RWC connect status change */
#define  EHCI_PS_CS		0x00000001 /* RO connect status */
#define  EHCI_PS_CLEAR		(EHCI_PS_OCC|EHCI_PS_PEC|EHCI_PS_CSC)
#define  EHCI_PS_NO_TEST	0x00000000 /* test mode not enabled */
#define  EHCI_PS_TEST_J		0x00010000 /* test J */
#define  EHCI_PS_TEST_K		0x00020000 /* test K */
#define  EHCI_PS_TEST_SE0	0x00030000 /* test SE0 */
#define  EHCI_PS_TEST_PACK	0x00040000 /* test packet */
#define  EHCI_PS_TEST_FE	0x00050000 /* test force enable */
/**********************************************************************/

/******************** Structures for aync list queue pointer ********************/
typedef unsigned int u_int32_t;

typedef u_int32_t ehci_link_t;
#define EHCI_LINK_TERMINATE	0x00000001
#define EHCI_LINK_TYPE(x)	((x) & 0x00000006)
#define  EHCI_LINK_ITD		0x0
#define  EHCI_LINK_QH		0x2
#define  EHCI_LINK_SITD		0x4
#define  EHCI_LINK_FSTN		0x6
#define EHCI_LINK_ADDR(x)	((x) &~ 0x1f)

typedef u_int32_t ehci_physaddr_t;

/* Queue Element Transfer Descriptor */
#define EHCI_QTD_NBUFFERS 5
typedef struct {
	ehci_link_t	qtd_next;
	ehci_link_t	qtd_altnext;
	u_int32_t	qtd_status;
#define EHCI_QTD_GET_STATUS(x)	(((x) >>  0) & 0xff)
#define EHCI_QTD_SET_STATUS(x)	((x) <<  0)
#define  EHCI_QTD_ACTIVE	0x80
#define  EHCI_QTD_HALTED	0x40
#define  EHCI_QTD_BUFERR	0x20
#define  EHCI_QTD_BABBLE	0x10
#define  EHCI_QTD_XACTERR	0x08
#define  EHCI_QTD_MISSEDMICRO	0x04
#define  EHCI_QTD_SPLITXSTATE	0x02
#define  EHCI_QTD_PINGSTATE	0x01
#define  EHCI_QTD_STATERRS	0x7c
#define EHCI_QTD_GET_PID(x)	(((x) >>  8) & 0x3)
#define EHCI_QTD_SET_PID(x)	((x) <<  8)
#define  EHCI_QTD_PID_OUT	0x0
#define  EHCI_QTD_PID_IN	0x1
#define  EHCI_QTD_PID_SETUP	0x2
#define EHCI_QTD_GET_CERR(x)	(((x) >> 10) &  0x3)
#define EHCI_QTD_SET_CERR(x)	((x) << 10)
#define EHCI_QTD_GET_C_PAGE(x)	(((x) >> 12) &  0x7)
#define EHCI_QTD_SET_C_PAGE(x)	((x) << 12)
#define EHCI_QTD_GET_IOC(x)	(((x) >> 15) &  0x1)
#define EHCI_QTD_IOC		0x00008000
#define EHCI_QTD_GET_BYTES(x)	(((x) >> 16) &  0x7fff)
#define EHCI_QTD_SET_BYTES(x)	((x) << 16)
#define EHCI_QTD_GET_TOGGLE(x)	(((x) >> 31) &  0x1)
#define	EHCI_QTD_SET_TOGGLE(x)	((x) << 31)
#define EHCI_QTD_TOGGLE_MASK	0x80000000
	ehci_physaddr_t	qtd_buffer[EHCI_QTD_NBUFFERS];
	ehci_physaddr_t qtd_buffer_hi[EHCI_QTD_NBUFFERS];
} ehci_qtd_t;
#define EHCI_QTD_ALIGN 32

/* Queue Head */
typedef struct {
	ehci_link_t	qh_link;
	u_int32_t	qh_endp;
#define EHCI_QH_GET_ADDR(x)	(((x) >>  0) & 0x7f) /* endpoint addr */
#define EHCI_QH_SET_ADDR(x)	(x)
#define EHCI_QH_ADDRMASK	0x0000007f
#define EHCI_QH_GET_INACT(x)	(((x) >>  7) & 0x01) /* inactivate on next */
#define EHCI_QH_INACT		0x00000080
#define EHCI_QH_GET_ENDPT(x)	(((x) >>  8) & 0x0f) /* endpoint no */
#define EHCI_QH_SET_ENDPT(x)	((x) <<  8)
#define EHCI_QH_GET_EPS(x)	(((x) >> 12) & 0x03) /* endpoint speed */
#define EHCI_QH_SET_EPS(x)	((x) << 12)
#define  EHCI_QH_SPEED_FULL	0x0
#define  EHCI_QH_SPEED_LOW	0x1
#define  EHCI_QH_SPEED_HIGH	0x2
#define EHCI_QH_GET_DTC(x)	(((x) >> 14) & 0x01) /* data toggle control */
#define EHCI_QH_DTC		0x00004000
#define EHCI_QH_GET_HRECL(x)	(((x) >> 15) & 0x01) /* head of reclamation */
#define EHCI_QH_HRECL		0x00008000
#define EHCI_QH_GET_MPL(x)	(((x) >> 16) & 0x7ff) /* max packet len */
#define EHCI_QH_SET_MPL(x)	((x) << 16)
#define EHCI_QH_MPLMASK		0x07ff0000
#define EHCI_QH_GET_CTL(x)	(((x) >> 27) & 0x01) /* control endpoint */
#define EHCI_QH_CTL		0x08000000
#define EHCI_QH_GET_NRL(x)	(((x) >> 28) & 0x0f) /* NAK reload */
#define EHCI_QH_SET_NRL(x)	((x) << 28)
	u_int32_t	qh_endphub;
#define EHCI_QH_GET_SMASK(x)	(((x) >>  0) & 0xff) /* intr sched mask */
#define EHCI_QH_SET_SMASK(x)	((x) <<  0)
#define EHCI_QH_GET_CMASK(x)	(((x) >>  8) & 0xff) /* split completion mask */
#define EHCI_QH_SET_CMASK(x)	((x) <<  8)
#define EHCI_QH_GET_HUBA(x)	(((x) >> 16) & 0x7f) /* hub address */
#define EHCI_QH_SET_HUBA(x)	((x) << 16)
#define EHCI_QH_GET_PORT(x)	(((x) >> 23) & 0x7f) /* hub port */
#define EHCI_QH_SET_PORT(x)	((x) << 23)
#define EHCI_QH_GET_MULT(x)	(((x) >> 30) & 0x03) /* pipe multiplier */
#define EHCI_QH_SET_MULT(x)	((x) << 30)
	ehci_link_t	qh_curqtd;
	ehci_qtd_t	qh_qtd;
} ehci_qh_t;
#define EHCI_QH_ALIGN 32
/********************************************************************************/
extern void usb_device_detect_test(void);
extern void malloc_init(void);
extern char * kmalloc(unsigned int , unsigned int );
extern void init_usbh(void);
void usb_electrical_test();
extern void runQueueHead(void);

extern void intctlInit(void);
extern void init_usb(void);
extern void event_usb(void);
/********************************************************************************/
				
		#ifdef     __cplusplus
}                       /* C declarations in C++     */
#endif