easic_pi.h.svn-base

Spearhead2000 的 USB驱动程序

/*****************************************************************************/
/* This confidential and proprietary software may be used only as authorized */
/* by a licensing agreement from STMicroelectronics.                         */
/* In the event of publication, the following notice is applicable:          */
/*                                                                           */
/*                   (C) COPYRIGHT 2002 STMicroelectronics                   */
/*                Innovative Systems Design Group - Central R&D              */
/*                            ALL RIGHTS RESERVED                            */
/*                                                                           */
/* The entire notice above must be reproduced on all authorized copies.      */
/*                                                                           */
/* -- File:                 ahbregs.h                                        */
/* -- Author:               Christian Gazzina  <[e-mail]>    */
/* -- Description:          Include file for general purpose ahb registers   */
/*                          test                                             */
/*                                                                           */
/* -- Modification History: - 1.1 (20/11/2002)                               */
/*                          - 1.2 (11/11/2003)                               */
/*                            - freeze                                       */
/*****************************************************************************/

// $Id: eASIC_PI.h,v 1.1 2005/06/27 14:15:39 sp_head Exp $

// $Log: eASIC_PI.h,v $
// Revision 1.1  2005/06/27 14:15:39  sp_head
// apb_configuration.h
//
// Revision 1.1.1.2  2004/12/03 15:34:24  spear
// First import from CRD
//
// Revision 1.1.1.1  2004/12/02 11:07:22  spear
// First import from CRD
//
// 
//  Revision: 1.1 Tue Nov 23 10:14:07 2004 gazzina
//  first release
// 
//  Revision: 1.2 Tue Nov 11 11:49:54 2003 gazzina
//  freeze
// 
//  Revision: 1.1 Fri Jul 18 11:47:14 2003 gazzina
//  first check in

#ifndef __EASIC_PI_H__
#define __EASIC_PI_H__
//  Registers description:
//  eASIC_PI_DATA : parallel data to be sent to eASIC
//  eASIC_PI_CTRL : 
//	   --
//	  | 0|--> Select_reg   : 1-->registri; 0-->DMA;
//	  | 1|--> reg_PI_resetn
//	  | 2|--> SU    --\                                        
//	  | 3|--> SWE   -- \                                       
//	  | 4|--> SRE   --  \  
//	  | 5|--> INC   --   > eASIC PI control signals                                             
//	  | 6|--> COMP  --  /                                      
//	  | 7|--> RSTC  -- /                                        
//	  | 8|--> XSCAN --/   
//	  | 9|--> Start_Serial --\                                        
//	  |10|--> Data_size(0) -- \                                      
//	  |11|--> Data_size(1) --  > Control signal for serializer       
//	  |12|--> Data_size(2) -- /                                      
//	  |13|--> Endianity    --/                                       
//	  |14|--> SD_line_sel(0) --\  
//	  |15|--> SD_line_sel(1) -- > They decide which serial line is 
//	  |16|--> SD_line_sel(2) --/  being programmed                 
//	  |17|--> Clock Gating : 0->clock not gated / 1->clock gated
//	  |18|--> Not used                                 
//	  |19|--> Not used
//	  |20|--> Not used
//	  |21|--> Not used
//	  |22|--> Not used
//	  |23|--> Not used
//-------------------------- SW read / HW write bits
//	  |24|--> Serial_busy       --> if 1 : programming in progress (data_valid signal)
//	  |25|--> Parallel_busy     --> if 1 : reading data from eASIC in progress
//	  |26|--> Not used
//	  |27|--> Not used
//	  |28|--> Not used
//	  |29|--> Not used
//	  |30|--> Not used
//	  |31|--> Not used
//	   --

#define AHB_AHBREGS_Base 0x13000000

typedef struct AHBREGS_STRUCT{
   unsigned int eASIC_PI_CTRL;
   unsigned int eASIC_PI_DATA0;
   unsigned int eASIC_PI_DATA1;
   unsigned int eASIC_PI_DATA2;
   unsigned int eASIC_PI_DATA3;
   unsigned int eASIC_PI_READ0;
   unsigned int eASIC_PI_READ1;
   unsigned int eASIC_PI_READ2;
   unsigned int eASIC_PI_READ3;
   unsigned int eASIC_DMA_CTRL;       
   unsigned int eASIC_DMA_START_ADDR;   
   unsigned int eASIC_DMA_TRANSFER_SZ;  
   unsigned int eASIC_DMA_STATUS;        
} AHBREGS_STRUCT;


#define AHBREGS ((volatile struct AHBREGS_STRUCT*)(AHB_AHBREGS_Base))

/* Mask definition */
#define CTRL_Select_reg     0x00000001   
#define CTRL_reg_PI_reset   0x00000002
#define CTRL_SU             0x00000004
#define CTRL_SWE            0x00000008
#define CTRL_SRE            0x00000010
#define CTRL_INC            0x00000020 
#define CTRL_COMP           0x00000040
#define CTRL_RSTC           0x00000080 
#define CTRL_XSCAN          0x00000100
#define CTRL_Start_Serial   0x00000200
#define CTRL_Data_size      0x00001C00 /* Enables the 3 bits */
   #define CTRL_Data_size_shf        10

#define CTRL_Endianity      0x00002000 
#define CTRL_SD_line_sel    0x0001C000 /* Enables the 5 bits */
   #define CTRL_SD_line_sel_shf     14  

#define CTRL_CLK_Gate       0x00020000  /* Clock gating */

#define CTRL_Serial_busy       0x01000000
#define CTRL_Parallel_busy     0x02000000

#define CTRL_PI_EXT            0x80000000 /* programmazione dall'esterno */

/***** End of mask definition **********/


/***** DMA mask definition **************/
#define CTRL_DMA_start         0x00000001
#define CTRL_DMA_abort         0x00000002
#define CTRL_DMA_enable_int    0x00000004
/***** End DMA mask definition **********/


/***** Constant Definition *************/
#define PI_SW_MODE  0 
#define PI_DMA_MODE 1 
#define PI_SCAN_MODE 2 

#define PI_SW_RST_YES   1
#define PI_SW_RST_NO    0

#define PI_LSB_FIRST    0
#define PI_MSB_FIRST    1

#define PI_Data_sz_Byte       0x00000000
#define PI_Data_sz_Half       0x00000400
#define PI_Data_sz_Word       0x00000800

//#define PI_ext_prog_en        1

#define PI_BITSTREAM_SZ       32768

#define NULL 0
/***** End Constant Definition *********/

#define n_eASIC_lines 4
#define n_eASIC_col   4

/* Definizioni colonne e righe presenti */
#define EN_COL_0
#define EN_COL_1
#define EN_COL_2
#define EN_COL_3

#define EN_ROW_0
#define EN_ROW_1
#define EN_ROW_2
#define EN_ROW_3
//#define EN_ROW_4
//#define EN_ROW_5
//#define EN_ROW_6
//#define EN_ROW_7


#endif  // End of inclusion control