apb_configuration.h.svn-base

Spearhead2000 的 USB驱动程序

/*****************************************************************************/
/* This confidential and proprietary software may be used only as authorized */
/* by a licensing agreement from STMicroelectronics.                         */
/* In the event of publication, the following notice is applicable:          */
/*                                                                           */
/*                   (C) COPYRIGHT 2004 STMicroelectronics                   */
/*                Innovative Systems Design Group - Central R&D              */
/*                            ALL RIGHTS RESERVED                            */
/*                                                                           */
/* The entire notice above must be reproduced on all authorized copies.      */
/*                                                                           */
/* -- File:                  apb_configuration.h                             */
/* -- Author:                Francesco Lertora  <[e-mail]>   */
/* -- Description:           Driver APB Register Bank                        */
/*                                                                           */
/*****************************************************************************/
/*                               miniPRICe                                   */
/*****************************************************************************/
/* -- Modification History: - 1.1 (10/11/2004)                               */
/*                            - first version for miniPRICe                  */
/*                          - 1.2 (24/11/2004)                               */
/*                            - eASIC_PROTECTION_PORT_REGISTER reviewed      */
/*                          - 1.3 (14/12/2004)                               */
/*                            - spear realignment                            */
/*                          - 1.4 (11/01/2005)                               */
/*                            - clk_48 handle                                */
/*****************************************************************************/

// $Id: apb_configuration.h,v 1.3 2005/07/15 09:56:27 sp_head Exp $

// $Log: apb_configuration.h,v $
// Revision 1.3  2005/07/15 09:56:27  sp_head
//
// apb address modified (USER MC)
//
// Revision 1.2  2005/07/15 07:25:42  gazzina
// modified the APBControl base register
//
// Revision 1.1  2005/06/27 14:27:04  sp_head
// apb_configuration.h
//
// Revision 1.3  2005/01/25 10:35:33  spear
//
// Added the delay_line registers.
//
// AV
//
// Revision 1.2  2005/01/12 13:47:33  spear
// added clock 48MHz handle
//
// 
//  Revision: 1.4 Wed Jan 12 15:13:35 2005 gazzina
//  enable_dma_port added
// 
//  Revision: 1.3 Tue Dec 14 15:06:47 2004 gazzina
//  spear realignment
// Revision 1.1.1.2  2004/12/03 15:34:24  spear
// First import from CRD
//
// Revision 1.1.1.1  2004/12/02 11:07:22  spear
// First import from CRD
//
// 
//  Revision: 1.2 Thu Dec  2 11:21:00 2004 gazzina
//  full master define added
// 
//  Revision: 1.1 Tue Nov 23 10:14:06 2004 gazzina
//  first release


#ifndef __APB_CONF_H__
#define __APB_CONF_H__

typedef struct APB_Conf_Struct
{
  unsigned int __fill0;   // Base + 0
  unsigned int __fill1;   // Base + 4
  unsigned int __fill2;   // Base + 8

  // <CHANGE_PLL_FREQ_OK BIT> "0000000" <PLL LOCK BIT>
  unsigned int Pll_Status_Reg; // Base + C

  unsigned int __fill3;   // Base + 10
  unsigned int __fill4;   // Base + 14
  unsigned int __fill5;   // Base + 18
  unsigned int __fill6;   // Base + 1c
  unsigned int __fill7;   // Base + 20
  unsigned int __fill8;   // Base + 24
  unsigned int __fill9;   // Base + 28

  // eASIC_PROTECTION_PORT_REGISTER -------------------------------------------
  // bit 0 : Enable eASIC Slave Port 1
  // bit 1 : Enable eASIC Slave Port 2
  // bit 2 : Enable eASIC Master Lite Port
  // bit 3 : Enable eASIC Master PL175 Port
  // bit 4 : Enable eASIC Master Full Port
  // bit 5 : Enable eASIC Full Slave Port
  // bit 6 : Enable eASIC Interrupts Port
  // bit 7 : Enable DTCM Port 
  // bit 8 : Enable Coprocessor Port
  // bit 9 : Enable GPIO Port

  unsigned int eASIC_PROTECTION_PORT_REGISTER; // Base + 2c

  // bit   7-0: FREQ. REFRESH DIVIDER FOR SDRAM (Default: 63)
  // bit  15-8: M VALUE FOR PLL91  (Default:  1) }
  // bit 23-16: N VALUE FOR PLL91  (Default: 20)  } Default Multiplication x20
  // bit 26-24: P VALUE FOR PLL91  (Default:  1) }
  // bit    31: CHANGE FREQUENCY BIT FOR PLL91
  unsigned int RESET_CLOCK_CONTROL_REGISTER; // Base + 30


  //////////////////////////////////////////////////////////////////////
  // PRESCALER                                                        //
  // I clock che posso controllare sono:                              //
  // - CLOCK PROG INT                                                 //
  //                                                                  //
  // I registri sono fisicamente a 20 bit (19 DOWNTO 0)               //
  // divisi in tre campi:                                             //
  // <11..0>  : 12 Bit - Valore M (Calcolo Frequenza)                 //
  // <15..12> :  4 Bit - Valore N (Calcolo Frequenza)                 //
  // <19..16> :  4 Bit - Shift                                        //
  // La Frequenza in uscita e' ottenuta tramite la seguente equazione://
  //                                                                  //
  //                    F_CLK_IN                                      //
  // F_CLK_OUT =  -------------------                                 //
  //               (N + 1)                                            //
  //              2        x  (M + 1)                                 //
  //                                                                  //
  // Esempio: DIVISIONE DI F_CLK_IN PER 6                             //
  // 6 non e' potenza di 2 ma si puo' ottenere come 2 x 3 => M = 2    //
  //                                                         N = 0    //
  // Lo Shif specifica dopo quanti cicli clock di 'F_CLK_IN' il       //
  // prescaler inizia a dividere.                                     //
  //                                                                  //______
  // Valore di default : HCLK / 4  
  //                                                                          //
  // --REGISTRO--------------------VALORE-------------DIVISIONE-----SHIFT-----//
  //                                                                          //
  // - PRESCALER_REGISTER_CK8      0x01000 (N=1)              2         0     //
  //                                       (M=0)                              //
  //                                                                          //
  //////////////////////////////////////////////////////////////////////////////
  unsigned int PRESCALER_REGISTER_CK_PI; // Base + 34

  unsigned int PRESCALER_REGISTER_CK_48; // Base + 38
  unsigned int __fill10;   // Base + 3c

  //////////////////////////////////////////////////////////////////////
  // ENABLE REGISTER                                                  //
  // Se il bit relativo dell'Enable register                          //
  // e' a '1' si abilita il gating da parte dell'ARM con              // 
  // il segnale DBACK. Questa e' la situazione di default.            // 
  // Se il bit e' a '0' allora il gating dipende dal Disable Register.//
  //////////////////////////////////////////////////////////////////////
  //CLK_ENABLE_REGISTER(0) : s_enable_clk_PI
  //CLK_ENABLE_REGISTER(1) : s_enable_HCLK_PI
  //CLK_ENABLE_REGISTER(2) : s_enable_clk_48
  unsigned int CLK_ENABLE_REGISTER;   // Base + 40
  
  //////////////////////////////////////////////////////////////////////
  // DISABLE REGISTER                                                 //
  // Prioritario rispetto all'enable register                         // 
  // nel senso che se un bit di questo registro e' a '1'              //
  // il segnale di enable viene ignorato e il clock gating e'         //
  // del tutto disabilitato                                           //
  //////////////////////////////////////////////////////////////////////
  //CLK_DISABLE_REGISTER(0) : s_disable_clk_PI
  //CLK_DISABLE_REGISTER(1) : s_disable_HCLK_PI
  //CLK_DISABLE_REGISTER(2) : s_disable_clk_48
  unsigned int CLK_DISABLE_REGISTER; // Base + 44
  unsigned int __fill11;   // Base + 48
  unsigned int __fill12;   // Base + 4c
  unsigned int SDRAM_OUTPUT_CLOCK_DELAY; // Base + 50
  unsigned int SDRAM_INTPUT_CLOCK_DELAY; // Base + 54
  unsigned int SDRAM_FB_CLOCK_SOURCE;    // Base + 58
} APB_Conf_Struct;

#define APBControl ((volatile struct APB_Conf_Struct *)(0x12003000))

// Define Gestione Clock ------------------------------------------------------
#define ENABLE_CLK_PI          0x00000001U
#define ENABLE_HCLK_PI         0x00000002U
#define ENABLE_CLK_48          0x00000004U

#define DISABLE_CLK_PI         0xFFFFFFFEU
#define DISABLE_HCLK_PI        0xFFFFFFFDU
#define DISABLE_CLK_48         0xFFFFFFFBU


// Defines For eASIC Protection Register --------------------------------------
#define ENABLE_eASIC_SLAVE_PORT_1      0x00000001U
#define ENABLE_eASIC_SLAVE_PORT_2      0x00000002U
#define ENABLE_eASIC_MASTER_LITE_PORT  0x00000004U
#define ENABLE_eASIC_MASTER_PL175_PORT 0x00000008U  
#define ENABLE_eASIC_MASTER_FULL_PORT  0x00000010U
#define ENABLE_eASIC_SLAVE_FULL_PORT   0x00000020U
#define ENABLE_eASIC_INTERRUPT_PORT    0x00000040U
#define ENABLE_eASIC_DCTM_PORT         0x00000080U
#define ENABLE_COPROC_PORT             0x00000100U
#define ENABLE_eASIC_GPIOs             0x00000200U
#define ENABLE_DMA_PORT                0x00000400U
#endif