dramc.h.svn-base

Spearhead2000 的 USB驱动程序

#ifndef __dramc_h
#define __dramc_h

//-----------------------------------------------------------------------------
//	DRAMC
//-----------------------------------------------------------------------------

#define DRAMC_BASE_ADDRESS      0x1000C000

typedef struct DRAMController
{
  unsigned int DMC_MB1Cfg;
  unsigned int DMC_MB2Cfg; 
  unsigned int DMC_MB3Cfg; 
  unsigned int DMC_MB4Cfg; 
  unsigned int DMC_SDRAM1CfgLO;
  unsigned int DMC_SDRAM1CfgHI; 
  unsigned int DMC_SDRAM2CfgLO; 
  unsigned int DMC_SDRAM2CfgHI; 
  unsigned int DMC_SDRAM3CfgLO; 
  unsigned int DMC_SDRAM3CfgHI; 
  unsigned int DMC_SDRAM4CfgLO; 
  unsigned int DMC_SDRAM4CfgHI; 
  unsigned int DMC_MemCfg;	
  unsigned int DMC_Size1;
  unsigned int DMC_Size2; 
  unsigned int DMC_Size3; 
  unsigned int DMC_Size4; 
} DRAMController;

// Memory Banks Cfguration Registers values
#define	DMC_8bitCol		0x0000	// 8bit column width 
#define	DMC_9bitCol		0x0001	// 9bit column width 
#define	DMC_10bitCol		0x0002	// 10bit column width 
#define	DMC_IdleTimeMask	0x001C	// (Field Mask) Minimum cycles the memdrv must spend in idle state
#define	DMC_IdleTimeU		0x0004	// (Field Base) Minimum cycles the memdrv must spend in idle state
#define	DMC_SetupTimeMask	0x00E0	// (Field Mask) Number of cycles spent in decoding state 
#define	DMC_SetupTimeU		0x0020	// (Field Base) Number of cycles spent in decoding state 
#define	DMC_DataLatMask		0x0300	// (Field Mask) Number of cycles between memory access and data available 
#define	DMC_DataLatU		0x0100	// (Field Base) Number of cycles between memory access and data available 
#define	DMC_8bitDev		0x0000	// External Memory Device width: 8 bit 
#define	DMC_16bitDev		0x0400	// External Memory Device width: 16 bit 
#define	DMC_32bitDev		0x0800	// External Memory Device width: 32 bit 

// Memory Size Configuration Register
#define	DMC_SizeUnit		0x0001 // Base Size Unit (in 64kb)

// Memory Configuration Registers values
#define	DMC_RefrMask		0x00FF	// (Field Mask) Refresh period (usecs) 
#define	DMC_RefrU		0x0001	// (Field Base) Refresh period (usecs) 
#define	DMC_Bank1OFF		0x0000	// Bank1 off 
#define	DMC_Bank1ON		0x0100	// Bank1 on 
#define	DMC_Bank2OFF		0x0000	// Bank2 off 
#define	DMC_Bank2ON		0x0200	// Bank2 on 
#define	DMC_Bank3OFF		0x0000	// Bank3 off 
#define	DMC_Bank3ON		0x0400	// Bank3 on 
#define	DMC_Bank4OFF		0x0000	// Bank4 off 
#define	DMC_Bank4ON		0x0800	// Bank4 on 
#define	DMC_EDOType		0x0000	// EDO type 
#define	DMC_SDRAMType		0x1000	// SDRAM type 
#define	DMC_PSnormal		0x0000	// Normal mode Power Save 
#define	DMC_PSself		0x2000	// Self-refresh mode Power Save 



#define DRAMCntl ((volatile struct DRAMController*) (DRAMC_BASE_ADDRESS))


#define DRAM_START_ADDRESS      0x00000000



#endif