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📁 Spearhead2000 的 USB驱动程序
💻 SVN-BASE
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DMASource_Lo_0	include/gdma.h	/^  unsigned int DMASource_Lo_0;$/;"	m	struct:DMA_Control_StructDMASource_Lo_1	include/gdma.h	/^  unsigned int DMASource_Lo_1;$/;"	m	struct:DMA_Control_StructDMASource_Lo_2	include/gdma.h	/^  unsigned int DMASource_Lo_2;$/;"	m	struct:DMA_Control_StructDMASource_Lo_3	include/gdma.h	/^  unsigned int DMASource_Lo_3;$/;"	m	struct:DMA_Control_StructDMAStatus	code/test_Siva/dma_hwp.h	/^	t_uint32 *DMAStatus;	            \/* A register used to get the information on the ongoing exchanges *\/\/*0x0F8*\/$/;"	m	struct:DMAStatus	include/gdma.h	/^  unsigned int DMAStatus;$/;"	m	struct:DMA_Control_StructDMATCnt_0	include/gdma.h	/^  unsigned int DMATCnt_0;$/;"	m	struct:DMA_Control_StructDMATCnt_1	include/gdma.h	/^  unsigned int DMATCnt_1;$/;"	m	struct:DMA_Control_StructDMATCnt_2	include/gdma.h	/^  unsigned int DMATCnt_2;$/;"	m	struct:DMA_Control_StructDMATCnt_3	include/gdma.h	/^  unsigned int DMATCnt_3;$/;"	m	struct:DMA_Control_StructDMA_AbortPipeExchanges	code/test_Siva/dma.c	/^PUBLIC t_dma_error DMA_AbortPipeExchanges(t_dma_pipe_id pipeId)$/;"	fDMA_BIG_ENDIAN_MODE	code/test_Siva/dmabase.h	/^	DMA_BIG_ENDIAN_MODE$/;"	eDMA_CH0	include/gdma.h	88;"	dDMA_CH1	include/gdma.h	89;"	dDMA_CH2	include/gdma.h	90;"	dDMA_CH3	include/gdma.h	91;"	dDMA_CHANNEL_0	code/test_Siva/dmabase.h	/^	DMA_CHANNEL_0 = 0,$/;"	eDMA_CHANNEL_1	code/test_Siva/dmabase.h	/^	DMA_CHANNEL_1,$/;"	eDMA_CHANNEL_2	code/test_Siva/dmabase.h	/^	DMA_CHANNEL_2,$/;"	eDMA_CHANNEL_3	code/test_Siva/dmabase.h	/^	DMA_CHANNEL_3$/;"	eDMA_CHANNEL_ALREADY_FREED	code/test_Siva/dma.h	/^DMA_CHANNEL_ALREADY_FREED,$/;"	eDMA_CHANNEL_CONTROL_REG_INIT	code/test_Siva/dma_hwp.h	155;"	dDMA_CHANNEL_UNDEFINED	code/test_Siva/dmabase.h	/^    DMA_CHANNEL_UNDEFINED = -1,$/;"	eDMA_CONTROLLER_DISABLE	code/test_Siva/dma_hwp.h	56;"	dDMA_CONTROLLER_ENABLE	code/test_Siva/dma_hwp.h	57;"	dDMA_ClearIRQSrc	code/test_Siva/dmairqmgt.c	/^PUBLIC void DMA_ClearIRQSrc( $/;"	fDMA_ClosePipe	code/test_Siva/dma.c	/^t_dma_error DMA_ClosePipe(t_dma_pipe_id pipeId)$/;"	fDMA_ConfigureDmaDevice	code/test_Siva/dma.c	/^PUBLIC t_dma_error DMA_ConfigureDmaDevice(t_dma_pipe_id pipeId,$/;"	fDMA_Control_Struct	include/gdma.h	/^typedef struct DMA_Control_Struct$/;"	sDMA_Control_Struct	include/gdma.h	/^} DMA_Control_Struct;$/;"	tDMA_Copy	code/test_Siva/dma.c	/^PUBLIC t_dma_error DMA_Copy(t_dma_pipe_id pipeId,$/;"	fDMA_DEST_DEVICE_NOT_CONFIGURED	code/test_Siva/dma.h	/^DMA_DEST_DEVICE_NOT_CONFIGURED,$/;"	eDMA_DEVICE_CANT_BE_FLOWCTRL	code/test_Siva/dma.h	/^DMA_DEVICE_CANT_BE_FLOWCTRL,  \/* SPEAR think over it *\/ $/;"	eDMA_DEVICE_NOT_CONFIGURABLE	code/test_Siva/dma.h	/^DMA_DEVICE_NOT_CONFIGURABLE,$/;"	eDMA_DMA_DEVICE_ALREADY_USED	code/test_Siva/dma.h	/^DMA_DMA_DEVICE_ALREADY_USED,$/;"	eDMA_DecDst	include/gdma.h	68;"	dDMA_DecSrc	include/gdma.h	65;"	dDMA_Dir	include/gdma.h	80;"	dDMA_DisableIRQSrc	code/test_Siva/dmairqmgt.c	/^PUBLIC void DMA_DisableIRQSrc( $/;"	fDMA_DstSzB	include/gdma.h	76;"	dDMA_DstSzH	include/gdma.h	77;"	dDMA_DstSzW	include/gdma.h	78;"	dDMA_ERROR	code/test_Siva/dma.h	/^DMA_ERROR = -1,$/;"	eDMA_EVENT_ERROR	code/test_Siva/dma.h	/^	DMA_EVENT_ERROR = MASK_BIT0, \/* ** Spear **bit 0 ? *\/$/;"	eDMA_EVENT_TC	code/test_Siva/dma.h	/^	DMA_EVENT_TC    = MASK_BIT1  \/*  *\/$/;"	eDMA_EXCHANGE_DESC_INIT	code/test_Siva/dmap.h	47;"	dDMA_Enab	include/gdma.h	62;"	dDMA_EnableIRQSrc	code/test_Siva/dmairqmgt.c	/^PUBLIC void DMA_EnableIRQSrc( $/;"	fDMA_FilterProcessIRQSrc	code/test_Siva/dma.c	/^PUBLIC t_dma_error DMA_FilterProcessIRQSrc( $/;"	fDMA_FixDst	include/gdma.h	66;"	dDMA_FixSrc	include/gdma.h	63;"	dDMA_GetDeviceId	code/test_Siva/dmairqmgt.c	/^PUBLIC t_dma_ctrl_id DMA_GetDeviceId( $/;"	fDMA_GetExchangeStatus	code/test_Siva/dma.c	/^PUBLIC t_dma_error DMA_GetExchangeStatus(t_dma_pipe_id pipeId,$/;"	fDMA_GetIRQSrc	code/test_Siva/dmairqmgt.c	/^PUBLIC t_dma_irq_src DMA_GetIRQSrc( $/;"	fDMA_GetIRQSrcStatus	code/test_Siva/dma.c	/^PUBLIC void DMA_GetIRQSrcStatus($/;"	fDMA_GetPipeStatus	code/test_Siva/dma.c	/^PUBLIC t_dma_error DMA_GetPipeStatus(t_dma_pipe_id pipeId,$/;"	fDMA_GetVersion	code/test_Siva/dma.c	/^PUBLIC t_dma_error DMA_GetVersion(t_version * pVersion)$/;"	fDMA_HCL_DBG_ID	code/test_Siva/debug.h	/^    DMA_HCL_DBG_ID,$/;"	eDMA_HCL_MAJOR_ID	code/test_Siva/dma.h	33;"	dDMA_HCL_MINOR_ID	code/test_Siva/dma.h	34;"	dDMA_HCL_VERSION_ID	code/test_Siva/dma.h	32;"	dDMA_INCOMPATIBLE_CONFIGURE_SIZE	code/test_Siva/dma.h	/^DMA_INCOMPATIBLE_CONFIGURE_SIZE,$/;"	eDMA_INCOMPATIBLE_DMA_DEVICE	code/test_Siva/dma.h	/^DMA_INCOMPATIBLE_DMA_DEVICE,$/;"	eDMA_INCOMPATIBLE_EXCHANGE_SIZE	code/test_Siva/dma.h	/^DMA_INCOMPATIBLE_EXCHANGE_SIZE,$/;"	eDMA_INCOMPATIBLE_EXCHANGE_TYPE	code/test_Siva/dma.h	/^DMA_INCOMPATIBLE_EXCHANGE_TYPE,$/;"	eDMA_INCOMPATIBLE_HW	code/test_Siva/dma.h	/^DMA_INCOMPATIBLE_HW,$/;"	eDMA_INCOMPATIBLE_PROTECTION_BITS	code/test_Siva/dma.h	/^DMA_INCOMPATIBLE_PROTECTION_BITS, \/* No protection is used in Spear *\/$/;"	eDMA_INCOMPATIBLE_TRANSFER_SIZE	code/test_Siva/dma.h	/^DMA_INCOMPATIBLE_TRANSFER_SIZE, $/;"	eDMA_INTERNAL_EVENT	code/test_Siva/dma.h	/^DMA_INTERNAL_EVENT           = HCL_INTERNAL_EVENT,$/;"	eDMA_IRQ_CHANNEL_0	code/test_Siva/dma.h	/^	DMA_IRQ_CHANNEL_0 = 0,$/;"	eDMA_IRQ_CHANNEL_1	code/test_Siva/dma.h	/^	DMA_IRQ_CHANNEL_1,$/;"	eDMA_IRQ_CHANNEL_2	code/test_Siva/dma.h	/^	DMA_IRQ_CHANNEL_2,$/;"	eDMA_IRQ_CHANNEL_3	code/test_Siva/dma.h	/^	DMA_IRQ_CHANNEL_3,$/;"	eDMA_IRQ_CHANNEL_4	code/test_Siva/dma.h	/^	DMA_IRQ_CHANNEL_4,$/;"	eDMA_IRQ_CHANNEL_5	code/test_Siva/dma.h	/^	DMA_IRQ_CHANNEL_5,$/;"	eDMA_IRQ_CHANNEL_6	code/test_Siva/dma.h	/^	DMA_IRQ_CHANNEL_6,$/;"	eDMA_IRQ_CHANNEL_7	code/test_Siva/dma.h	/^	DMA_IRQ_CHANNEL_7,$/;"	eDMA_IRQ_CHANNEL_8	code/test_Siva/dma.h	/^	DMA_IRQ_CHANNEL_8$/;"	eDMA_IRQ_CHANNEL_MIN1	code/test_Siva/dma.h	/^	DMA_IRQ_CHANNEL_MIN1 = -1,$/;"	eDMA_IncDst	include/gdma.h	67;"	dDMA_IncSrc	include/gdma.h	64;"	dDMA_Init	code/test_Siva/dma.c	/^PUBLIC t_dma_error DMA_Init(t_logical_address dma1LogicalBaseAddr,$/;"	fDMA_IsDmaDeviceConfigurationNeeded	code/test_Siva/dma.c	/^PUBLIC t_bool DMA_IsDmaDeviceConfigurationNeeded$/;"	fDMA_IsEventActive	code/test_Siva/dma.c	/^PUBLIC t_bool DMA_IsEventActive($/;"	fDMA_IsIRQSrcActive	code/test_Siva/dma.c	/^PUBLIC t_bool DMA_IsIRQSrcActive($/;"	fDMA_IsPendingIRQSrc	code/test_Siva/dmairqmgt.c	/^PUBLIC t_bool DMA_IsPendingIRQSrc( $/;"	fDMA_LAST_ERROR	code/test_Siva/dma.h	/^DMA_LAST_ERROR = -128,$/;"	eDMA_LITTLE_ENDIAN_MODE	code/test_Siva/dmabase.h	/^	DMA_LITTLE_ENDIAN_MODE,$/;"	eDMA_MAX_TRANSFER_SIZE	code/test_Siva/dma_hwp.h	134;"	dDMA_MISALIGNED_MEMORY_ADDR	code/test_Siva/dma.h	/^DMA_MISALIGNED_MEMORY_ADDR,$/;"	eDMA_MISSING_CONFIGURE_PARAMETER	code/test_Siva/dma.h	/^DMA_MISSING_CONFIGURE_PARAMETER,$/;"	eDMA_Mem2Mem	include/gdma.h	79;"	dDMA_NONE_REQUEST	code/test_Siva/dmabase.h	/^	DMA_NONE_REQUEST = 0xFF$/;"	eDMA_NOT_EVEN_EXCHANGE_REQUEST	code/test_Siva/dma.h	/^DMA_NOT_EVEN_EXCHANGE_REQUEST,$/;"	eDMA_NOT_MULTIPLE_SIZE_REQUEST	code/test_Siva/dma.h	/^DMA_NOT_MULTIPLE_SIZE_REQUEST,$/;"	eDMA_NO_MORE_HW_CHANNELS_AVAILABLE	code/test_Siva/dma.h	/^DMA_NO_MORE_HW_CHANNELS_AVAILABLE,$/;"	eDMA_NO_MORE_LLIS_AVAILABLE	code/test_Siva/dma.h	/^DMA_NO_MORE_LLIS_AVAILABLE,			\/* must get deleted *\/$/;"	eDMA_NO_MORE_PENDING_EVENT	code/test_Siva/dma.h	/^DMA_NO_MORE_PENDING_EVENT    = HCL_NO_MORE_PENDING_EVENT,$/;"	eDMA_NO_MORE_PIPE_AVAILABLE	code/test_Siva/dma.h	/^DMA_NO_MORE_PIPE_AVAILABLE,$/;"	eDMA_NO_PENDING_EVENT_ERROR	code/test_Siva/dma.h	/^DMA_NO_PENDING_EVENT_ERROR   = HCL_NO_PENDING_EVENT_ERROR,$/;"	eDMA_OK	code/test_Siva/dma.h	/^DMA_OK = 0,$/;"	eDMA_ONGOING_EXCHANGE	code/test_Siva/dma.h	/^DMA_ONGOING_EXCHANGE,$/;"	eDMA_OpenPipe	code/test_Siva/dma.c	/^PUBLIC t_dma_pipe_id DMA_OpenPipe(t_dma_device_id srcDeviceId,$/;"	fDMA_PERIPHERAL_ID	code/test_Siva/dmaconfigp.h	39;"	dDMA_PERIPHERAL_ID	code/test_Siva/dmaconfigp.h	52;"	dDMA_PIPES_MAX_NUM	code/test_Siva/dma.h	39;"	dDMA_PRIMECELL_ID	code/test_Siva/dmaconfigp.h	40;"	dDMA_PRIMECELL_ID	code/test_Siva/dmaconfigp.h	53;"	dDMA_REMAINING_PENDING_EVENTS	code/test_Siva/dma.h	/^DMA_REMAINING_PENDING_EVENTS = HCL_REMAINING_PENDING_EVENTS,$/;"	eDMA_REQUEST_0	code/test_Siva/dmabase.h	/^	DMA_REQUEST_0,$/;"	eDMA_REQUEST_1	code/test_Siva/dmabase.h	/^	DMA_REQUEST_1,$/;"	eDMA_REQUEST_10	code/test_Siva/dmabase.h	/^	DMA_REQUEST_10,$/;"	eDMA_REQUEST_11	code/test_Siva/dmabase.h	/^	DMA_REQUEST_11,$/;"	eDMA_REQUEST_12	code/test_Siva/dmabase.h	/^	DMA_REQUEST_12,$/;"	eDMA_REQUEST_13	code/test_Siva/dmabase.h	/^	DMA_REQUEST_13,$/;"	eDMA_REQUEST_14	code/test_Siva/dmabase.h	/^	DMA_REQUEST_14,$/;"	eDMA_REQUEST_15	code/test_Siva/dmabase.h	/^	DMA_REQUEST_15,$/;"	eDMA_REQUEST_2	code/test_Siva/dmabase.h	/^	DMA_REQUEST_2,$/;"	eDMA_REQUEST_3	code/test_Siva/dmabase.h	/^	DMA_REQUEST_3,$/;"	eDMA_REQUEST_4	code/test_Siva/dmabase.h	/^	DMA_REQUEST_4,$/;"	eDMA_REQUEST_5	code/test_Siva/dmabase.h	/^	DMA_REQUEST_5,$/;"	eDMA_REQUEST_6	code/test_Siva/dmabase.h	/^	DMA_REQUEST_6,$/;"	eDMA_REQUEST_7	code/test_Siva/dmabase.h	/^	DMA_REQUEST_7,$/;"	eDMA_REQUEST_8	code/test_Siva/dmabase.h	/^	DMA_REQUEST_8,$/;"	eDMA_REQUEST_9	code/test_Siva/dmabase.h	/^	DMA_REQUEST_9,$/;"	eDMA_REQUEST_QUEUED	code/test_Siva/dma.h	/^DMA_REQUEST_QUEUED = 15$/;"	eDMA_REQUEST_QUEUING_OVERFLOW	code/test_Siva/dma.h	/^DMA_REQUEST_QUEUING_OVERFLOW,$/;"	eDMA_Receive	code/test_Siva/dma.c	/^PUBLIC t_dma_error DMA_Receive(t_dma_pipe_id pipeId,$/;"	fDMA_S0Irq	include/gdma.h	83;"	dDMA_S1Irq	include/gdma.h	84;"	dDMA_S2Irq	include/gdma.h	85;"	dDMA_S3Irq	include/gdma.h	86;"	dDMA_SRC_DEVICE_NOT_CONFIGURED	code/test_Siva/dma.h	/^DMA_SRC_DEVICE_NOT_CONFIGURED,$/;"	eDMA_SRC_DEVICE_SHALL_BE_CONFIGURED_FIRST	code/test_Siva/dma.h	/^DMA_SRC_DEVICE_SHALL_BE_CONFIGURED_FIRST,$/;"	eDMA_SetBaseAddress	code/test_Siva/dmairqmgt.c	/^PUBLIC void DMA_SetBaseAddress($/;"	fDMA_SetPipeFlowController	code/test_Siva/dma.c	/^PUBLIC t_dma_error DMA_SetPipeFlowController(t_dma_pipe_id pipeId,$/;"	fDMA_SrcBst1	include/gdma.h	72;"	dDMA_SrcBst16	include/gdma.h	75;"	dDMA_SrcBst4	include/gdma.h	73;"	dDMA_SrcBst8	include/gdma.h	74;"	dDMA_SrcSzB	include/gdma.h	69;"	dDMA_SrcSzH	include/gdma.h	70;"	dDMA_SrcSzW	include/gdma.h	71;"	dDMA_Transmit	code/test_Siva/dma.c	/^PUBLIC t_dma_error DMA_Transmit(t_dma_pipe_id pipeId,$/;"	fDMA_UNKNOWN_DEVICE_ID	code/test_Siva/dma.h	/^DMA_UNKNOWN_DEVICE_ID,$/;"	eDMA_UNKNOWN_EXCHANGE_ID	code/test_Siva/dma.h	/^DMA_UNKNOWN_EXCHANGE_ID,$/;"	eDMA_UNKNOWN_PIPE_ID	code/test_Siva/dma.h	/^DMA_UNKNOWN_PIPE_ID,$/;"	eDMC_10bitCol	include/dramc.h	34;"	dDMC_16bitDev	include/dramc.h	42;"	dDMC_32bitDev	include/dramc.h	43;"	dDMC_8bitCol	include/dramc.h	32;"	dDMC_8bitDev	include/dramc.h	41;"	dDMC_9bitCol	include/dramc.h	33;"	dDMC_Bank1OFF	include/dramc.h	51;"	dDMC_Bank1ON	include/dramc.h	52;"	dDMC_Bank2OFF	include/dramc.h	53;"	dDMC_Bank2ON	include/dramc.h	54;"	dDMC_Bank3OFF	include/dramc.h	55;"	dDMC_Bank3ON	include/dramc.h	56;"	dDMC_Bank4OFF	include/dramc.h	57;"	dDMC_Bank4ON	include/dramc.h	58;"	dDMC_DataLatMask	include/dramc.h	39;"	dDMC_DataLatU	include/dramc.h	40;"	dDMC_EDOType	include/dramc.h	59;"	dDMC_IdleTimeMask	include/dramc.h	35;"	dDMC_IdleTimeU	include/dramc.h	36;"	dDMC_MB1Cfg	include/dramc.h	/^  unsigned int DMC_MB1Cfg;$/;"	m	struct:DRAMControllerDMC_MB2Cfg	include/dramc.h	/^  unsigned int DMC_MB2Cfg; $/;"	m	struct:DRAMControllerDMC_MB3Cfg	include/dramc.h	/^  unsigned int DMC_MB3Cfg; $/;"	m	struct:DRAMControllerDMC_MB4Cfg	include/dramc.h	/^  unsigned int DMC_MB4Cfg; $/;"	m	struct:DRAMControllerDMC_MemCfg	include/dramc.h	/^  unsigned int DMC_MemCfg;	$/;"	m	struct:DRAMControllerDMC_PSnormal	include/dramc.h	61;"	dDMC_PSself	include/dramc.h	62;"	dDMC_RefrMask	include/dramc.h	49;"	dDMC_RefrU	include/dramc.h	50;"	dDMC_SDRAM1CfgHI	include/dramc.h	/^  unsigned int DMC_SDRAM1CfgHI; $/;"	m	struct:DRAMControllerDMC_SDRAM1CfgLO	include/dramc.h	/^  unsigned int DMC_SDRAM1CfgLO;$/;"	m	struct:DRAMControllerDMC_SDRAM2CfgHI	include/dramc.h	/^  unsigned int DMC_SDRAM2CfgHI; $/;"	m	struct:DRAMControllerDMC_SDRAM2CfgLO	include/dramc.h	/^  unsigned int DMC_SDRAM2CfgLO; $/;"	m	struct:DRAMControllerDMC_SDRAM3CfgHI	include/dramc.h	/^  unsigned int DMC_SDRAM3CfgHI; $/;"	m	struct:DRAMControllerDMC_SDRAM3CfgLO	include/dramc.h	/^  unsigned int DMC_SDRAM3CfgLO; $/;"	m	struct:DRAMControllerDMC_SDRAM4CfgHI	include/dramc.h	/^  unsigned int DMC_SDRAM4CfgHI; $/;"	m	struct:DRAMControllerDMC_SDRAM4CfgLO	include/dramc.h	/^  unsigned int DMC_SDRAM4CfgLO; $/;"	m	struct:DRAMControllerDMC_SDRAMType	include/dramc.h	60;"	dDMC_SetupTimeMask	include/dramc.h	37;"	dDMC_SetupTimeU	include/dramc.h	38;"	dDMC_Size1	include/dramc.h	/^  unsigned int DMC_Size1;$/;"	m	struct:DRAMControllerDMC_Size2	include/dramc.h	/^  unsigned int DMC_Size2; $/;"	m	struct:DRAMControllerDMC_Size3	include/dramc.h	/^  unsigned int DMC_Size3; $/;"	m	struct:DRAMControllerDMC_Size4	include/dramc.h	/^  unsigned int DMC_Size4; $/;"	m	struct:DRAMControllerDMC_SizeUnit	include/dramc.h	46;"	dDOUBLE_BUFFERED	code/test_Siva/dma.h	/^	DOUBLE_BUFFERED$/;"	eDR	include/i2c.h	/^  unsigned int DR;   $/;"	m	struct:I2CControllerDRAMC_BASE_ADDRESS	include/dramc.h	8;"	dDRAMCntl	include/dramc.h	66;"	dDRAMController	include/dramc.h	/^typedef struct DRAMController$/;"	sDRAMController	include/dramc.h	/^} DRAMController;$/;"	tDRAM_START_ADDRESS	include/dramc.h	69;"	dDSEL_TIME	code/test_SMI/smi.h	67;"	dDSEL_TIME	code/test_SMI_NEW/smi.h	71;"	dDSEL_TIME	include/smi.h	67;"	dDTCMCntl_BYTE	include/dtcm_drv.h	56;"	dDTCMCntl_WORD	include/dtcm_drv.h	55;"	dDTCM_Base	include/dtcm_drv.h	41;"	dDTCM_MEMORY_SIZE_BYTE	include/dtcm_drv.h	45;"	dDTCM_MEMORY_SIZE_WORD	include/dtcm_drv.h	44;"	dDTCM_Memory_BYTE	include/dtcm_drv.h	/^typedef struct DTCM_Memory_BYTE{$/;"	sDTCM_Memory_BYTE	include/dtcm_drv.h	/^} DTCM_Memory_BYTE;$/;"	tDTCM_Memory_WORD	include/dtcm_drv.h	/^typedef struct DTCM_Memory_WORD{$/;"	s
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