spear_ddr.cmm

SpearHead的DDRRAM初始化脚本

;NOT YET CHANGED (YES ADDRESS, NO FREQUENCY)
;******************************
;*   Sys Init (HCLK = 75MHz)  *
;******************************
;set_pll_p_value = 1
;set_pll_p_value = 12
;set_pll_p_value = 150

;DATA.SET 0x12003044 %LE %LONG 1

;DATA.SET 0x12003044 %LE %LONG 3

;DATA.SET 0x12003030 %LE %LONG 0x0110013D

;DATA.SET 0x12003030 %LE %LONG 0x01100C3D

;DATA.SET 0x12003030 %LE %LONG 0x01960C3D

;DATA.SET 0x12003030 %LE %LONG 0x81960C3D

;WAIT 200ms

;SYSTEM.UP


;NOT YET CHANGED (YES ADDRESS, NO FREQUENCY)
;****************************
;*   Setting Dleay Lines    *
;****************************
;Input Delay line setting
;D.S SD:0x12003054 %LONG 0x40
;Output Delay line setting
;D.S SD:0x12003050 %LONG 0x40


;**********************
;*    Setting Remap   *
;**********************
;D.S SD:0x1200306c %LONG 0x01

; NOT YET ADDED
;********************************
;* Setting Mem Dimension (32MB) *
;********************************
;D.S SD:0x12003010 %LONG 0x02000000

;**************************
;*   Setting for PL175    *
;**************************
; PL175 reset
;D.S SD:0x12006000 %LONG 0x0
;D.S SD:0x12006024 %LONG 0x0

; Initial wait 100 us to ensure stable power, colck
;wait 1.ms

;Set normal memory map
;D.S SD:0x1000C000 %LONG 0x1

;Set Dynamic memory clock enable
D.S SD:0x1000C020 %LONG 0x018B

; Wait 200 us
;wait 1.ms

;Init Value to PALL
;D.S SD:0x12006024 %LONG 0x1
D.S SD:0x1000C020 %LONG 0x010B
;D.S SD:0x12006024 %LONG 0x0

;Set initial refresh timer value
D.S SD:0x1000C024 %LONG 0x2

;Wait 40 us perform refresh cycles
wait 1.ms

;PL175_DYNAMIC_REFRESH_TIME_INIT   EQU 50
;Set operational refresh timer value
D.S SD:0x1000C024 %LONG 0x32

;Set endianity
D.S SD:0x1000C008 %LONG 0x0

;WORST 1313
;BEST 1212
;set data strategy
;D.S SD:0x1000C028 %LONG 0x1313
D.S SD:0x1000C028 %LONG 0x0000


;set dynamic TRP
D.S SD:0x1000C030 %LONG 0x2

;set Dynamic TRAS
D.S SD:0x1000C034 %LONG 0x5

;set Dynamic TSRESX
D.S SD:0x1000C038 %LONG 0x6

;set Dynamic TWR
D.S SD:0x1000C044 %LONG 0x2

;set Dynamic TRC
D.S SD:0x1000C048 %LONG 0x8

;set Dynamic TRFC
D.S SD:0x1000C04C %LONG 0x8

;set Dynamic TXSR
D.S SD:0x1000C050 %LONG 0x6

;set Dynamic TRRD
D.S SD:0x1000C054 %LONG 0x2

;set Dynamic TMRD
D.S SD:0x1000C058 %LONG 0x2

;set Dynamic TCDLR
D.S SD:0x1000C05C %LONG 0xF

;set RAS CAS Latency
D.S SD:0x1000C104 %LONG 0x0282

;PL175 config to MODE
D.S SD:0x1000C100 %LONG 0x0684
D.S SD:0x1000C020 %LONG 0x008B

;Access to Mode register 0x21
D.IN 00000400 /LONG
wait 1ms
D.IN 00061000 /LONG

;Wait 200 us
wait 1.ms

;Init Value to PALL
D.S SD:0x1000C020 %LONG 0x010B

;Wait 40 us 
wait 1.ms

;Select Command Write Mode
D.S SD:0x1000C020 %LONG 0x008B

;;; NOT PRESENT
; LDR	 a1, =uDDRResetModeConfig
; CMP	 a1, #0x0
; LDRNE   a2, [a1, #0]

;Select Normal Write Mode
D.S SD:0x1000C020 %LONG 0x000B

;**************************

;Show Sdram Locations
;D.DUMP 0x00000000