crc.txt

循环冗余校验码CRC的VerilogHDL源程序

Module crc5(clk,
            rst_n,
            sdata,
            dload, 
            datacrco,
            hsend,
            datacrci,
            hrecv,rdata,
            dfinish,
            error);
input       clk;
input       rst_n;
input[11:0] sdata;
input       dload;
output[16:0] datacrco;
output      hsend;
input[16:0] datacrci;
input       hrecv;
output[11:0] rdata;
output      dfinish;
output      error;
reg[16:0]   datacrco_r;
reg         hsend_r;
reg[11:0]   rdata_r;
reg         dfinish_r;
reg         error_r;
reg[11:0]   dtemp;
reg[11:0]   sdtemp;
reg[11:0]   rdtemp;
reg[16:0]   rdatacrc;
parameter   polynomial = 6'b110101;
assign datacrco = datacrco_r;
assign hsend = hsend_r;
assign rdata = rdata_r;
assign dfinish = dfinish_r;
assign error = error_r;

always @ (posedge clk or negedge rst_n)
begin
    if(!rst_n)
    begin
        hsend_r = 1'b0;
        datacrco_r = 17'd0;
    end
    else if(dload == 1'b1)
    begin
        if(dtemp[11]) dtemp[11:6] = dtemp[11:6] ^ polynomial;
        if(dtemp[10]) dtemp[10:5] = dtemp[10:5] ^ polynomial;
        if(dtemp[9]) dtemp[9:4] = dtemp[9:4] ^ polynomial;
        if(dtemp[8]) dtemp[8:3] = dtemp[8:3] ^ polynomial; 
        if(dtemp[7]) dtemp[7:2] = dtemp[7:2] ^ polynomial;
        if(dtemp[6]) dtemp[6:1] = dtemp[6:1] ^ polynomial;
        if(dtemp[5]) dtemp[5:0] = dtemp[5:0] ^ polynomial;
        datacrco_r = {sdtemp,dtemp[4:0]};
        hsend_r = 1'b1;
    end
    else
        hsend_r = 1'b0;
end
always @ (posedge clk or negedge rst_n)
begin
    if(!rst_n)
    begin
        rdata_r =12'd0; 
        dfinish_r = 1'b0;
        error_r = 1'b0;
    end
    else if(hrecv == 1'b1)
    begin
        rdatacrc = datacrci;
        rdtemp = datacrci[16:5];
        if(rdtemp[11]) rdtemp[11:6] = rdtemp[11:6] ^ polynomial;
        if(rdtemp[10]) rdtemp[10:5] = rdtemp[10:5] ^ polynomial;
        if(rdtemp[9]) rdtemp[9:4] = rdtemp[9:4] ^ polynomial;
        if(rdtemp[8]) rdtemp[8:3] = rdtemp[8:3] ^ polynomial; 
        if(rdtemp[7]) rdtemp[7:2] = rdtemp[7:2] ^ polynomial;
        if(rdtemp[6]) rdtemp[6:1] = rdtemp[6:1] ^ polynomial;
        if(rdtemp[5]) rdtemp[5:0] = rdtemp[5:0] ^ polynomial;
        if(rdtemp[4:0] ^ rdatacrc[4:0] == 5'd0)
        begin
            rdata_r = rdatacrc[16:5];
            dfinish_r = 1'b1;
        end
        else
        begin
            rdata_r = 12'd0;
            error_r = 1'b1;
        end
    end
    else
        dfinish_r = 1'b0;
end
endmodule