lib_arm926ej_s.h

lcd mmu led 的相关测试

//*----------------------------------------------------------------------------
//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
//*----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*----------------------------------------------------------------------------
//* File Name           : mmu.c
//* Object              : Common MMU and CACHE operations
//* Creation            : GGi   March 10 2005
//*
//*----------------------------------------------------------------------------
// ****************************************************************************
// CP15 Register 0
// 	Read: ID code | cache type
//	Write: Unpredictable
#include <inarm.h>
#pragma inline=forced
#define __inline inline

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_ReadIDCode
//* \brief Read ID code register
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_ARM_ReadIDCode()
{
	register unsigned int id;
 	id = __MRC(15, 0, 0, 0, 0);
 	return id;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_ReadCacheType
//* \brief Read cache type
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_ARM_ReadCacheType()
{
	register unsigned int type;
 	type = __MRC(15, 0, 0, 0, 1);
 	return type;
}

// ****************************************************************************
// CP15 Register 1
// 	Read: Control
//	Write: Control

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_ReadControl
//* \brief Read Control register
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_ARM_ReadControl()
{
	register unsigned int ctl;
  ctl = __MRC(15, 0, 1, 0, 0);
 	return ctl;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_WriteControl
//* \brief Write Control register
//*----------------------------------------------------------------------------
__inline void AT91F_ARM_WriteControl(unsigned int ctl)
{
 	__MCR (15, 0, ctl, 1, 0, 0);
}

// ****************************************************************************
// CP15 Register 2
// 	Read: Translation table Base
//	Write: Translation table Base

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_ReadTTB
//* \brief Read Translation table base register
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_ARM_ReadTTB()
{
	register unsigned int ttb;
 	ttb = __MRC(15, 0, 2, 0, 0);
 	return ttb;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_WriteTTB
//* \brief Write Translation table base  register
//*----------------------------------------------------------------------------
__inline void AT91F_ARM_WriteTTB(unsigned int ttb)
{
 	__MCR (15, 0, (ttb & 0xFFFFC000), 2, 0, 0);
}

// ****************************************************************************
// CP15 Register 3
// 	Read: Read domain access control
//	Write: Write domain access control

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_ReadDomain
//* \brief Read domain access control
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_ARM_ReadDomain()
{
	register unsigned int domain;
 	domain = __MRC(15, 0, 3, 0, 0);
 	return domain;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_WriteDomain
//* \brief Write domain access control
//*----------------------------------------------------------------------------
__inline void AT91F_ARM_WriteDomain(unsigned int domain)
{
 	__MCR (15, 0, domain, 3, 0, 0);
}

// ****************************************************************************
// CP15 Register 5
// 	Read: Read Fault Status
//	Write: Write Fault Status

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_ReadDataFSR
//* \brief Read data FSR value
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_ARM_ReadDataFSR()
{
	register unsigned int dataFSR;
 	dataFSR = __MRC (15, 0, 5, 0, 0);
 	return dataFSR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_WriteDataFSR
//* \brief Write data FSR value
//*----------------------------------------------------------------------------
__inline void AT91F_ARM_WriteDataFSR(unsigned int dataFSR)
{
 	__MCR (15, 0, dataFSR, 5, 0, 0);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_ReadPrefetchFSR
//* \brief Read prefetch FSR value
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_ARM_ReadPrefetchFSR()
{
	register unsigned int prefetchFSR;
 	prefetchFSR = __MRC(15, 0, 5, 0, 1);
 	return prefetchFSR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_WritePrefetchFSR
//* \brief Write prefetch FSR value
//*----------------------------------------------------------------------------
__inline void AT91F_ARM_WritePrefetchFSR(unsigned int prefetchFSR)
{
 	__MCR (15, 0, prefetchFSR, 5, 0, 1);
}

// ****************************************************************************
// CP15 Register 6
// 	Read: Read Fault Address
//	Write: Write Fault Address

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_ReadFAR
//* \brief Read FAR data
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_ARM_ReadFAR()
{
	register unsigned int dataFAR;
 	dataFAR = __MRC (15, 0, 6, 0, 0);
 	return dataFAR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_WriteFAR
//* \brief Write FAR data
//*----------------------------------------------------------------------------
__inline void AT91F_ARM_WriteFAR(unsigned int dataFAR)
{
 	__MCR (15, 0, dataFAR, 6, 0, 0);
}

// ****************************************************************************
// CP15 Register 7
// 	Read: Unpredictable
//	Write: Cache operations

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_InvalidateIDCache
//* \brief Invalidate ICache and DCache
//*----------------------------------------------------------------------------
__inline void AT91F_ARM_InvalidateIDCache()
{
	register unsigned int sbz = 0;
 	__MCR (15, 0, sbz, 7, 7, 0);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_InvalidateICache
//* \brief Invalidate ICache
//*----------------------------------------------------------------------------
__inline void AT91F_ARM_InvalidateICache()
{
	register unsigned int sbz = 0;
 	__MCR (15, 0, sbz, 7, 5, 0);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_InvalidateICacheMVA
//* \brief Invalidate ICache single entry (using MVA)
//*----------------------------------------------------------------------------
__inline void AT91F_ARM_InvalidateICacheMVA(unsigned int mva)
{
 	__asm("MCR p15, 0, (mva & 0xFFFFFFE0), c7, c5, 1");
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_PrefetchICacheLine
//* \brief Prefetch ICache line (using MVA)
//*----------------------------------------------------------------------------
__inline void AT91F_ARM_PrefetchICacheLine(unsigned int mva)
{
 	__MCR (15, 0, (mva & 0xFFFFFFE0), 7, 13, 1);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_InvalidateDCache
//* \brief Invalidate DCache
//*----------------------------------------------------------------------------
__inline void AT91F_ARM_InvalidateDCache()
{
	register unsigned int sbz = 0;
 	__MCR (15, 0, sbz, 7, 6, 0);