movl.s

gdb-6.8 Linux下的调试程序 最新版本

	;; Now check the result of the move to memory.
	cmp.l	#0xcafedead, @long_dst
	beq	.Lnext30
	fail
.Lnext30:
	mov.l	#0, @long_dst	; zero it again for the next use.

.endif

	;;
	;; Move long from register source
	;; 

mov_l_reg32_to_reg32:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.l ers, erd
	mov.l	#0x12345678, er1
	mov.l	er1, er0	; Register 32-bit operand
;;;	.word	0x0f90

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear
	test_h_gr32 0x12345678 er0
	test_h_gr32 0x12345678 er1	; mov src unchanged

	test_gr_a5a5 2		; Make sure other general regs not disturbed
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

mov_l_reg32_to_indirect:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.l ers, @erd
	mov.l	#long_dst, er1
	mov.l	er0, @er1	; Register indirect operand
;;;	.word	0x0100
;;;	.word	0x6990

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	long_dst, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	mov.l	#0, er0
	mov.l	@long_dst, er0
	cmp.l	er2, er0
	beq	.Lnext44
	fail
.Lnext44:
	mov.l	#0, er0
	mov.l	er0, @long_dst	; zero it again for the next use.

.if (sim_cpu == h8sx)
mov_l_reg32_to_postinc:		; post-increment from register to mem
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.l ers, @erd+
	mov.l	#long_dst, er1
	mov.l	er0, @er1+	; Register post-incr operand
;;;	.word	0x0103
;;;	.word	0x6d90

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	long_dst+4, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	er2, @long_dst
	beq	.Lnext49
	fail
.Lnext49:
	mov.l	#0, @long_dst	; zero it again for the next use.

mov_l_reg32_to_postdec:		; post-decrement from register to mem
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.l ers, @erd-
	mov.l	#long_dst, er1
	mov.l	er0, @er1-	; Register post-decr operand
;;;	.word	0x0101
;;;	.word	0x6d90

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	long_dst-4, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	er2, @long_dst
	beq	.Lnext50
	fail
.Lnext50:
	mov.l	#0, @long_dst	; zero it again for the next use.

mov_l_reg32_to_preinc:		; pre-increment from register to mem
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.l ers, @+erd
	mov.l	#long_dst-4, er1
	mov.l	er0, @+er1	; Register pre-incr operand
;;;	.word	0x0102
;;;	.word	0x6d90

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	long_dst, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	er2, @long_dst
	beq	.Lnext51
	fail
.Lnext51:
	mov.l	#0, @long_dst	; zero it again for the next use.
.endif				; h8sx

mov_l_reg32_to_predec:		; pre-decrement from register to mem
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.l ers, @-erd
	mov.l	#long_dst+4, er1
	mov.l	er0, @-er1	; Register pre-decr operand
;;;	.word	0x0100
;;;	.word	0x6d90

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	long_dst, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	mov.l	#0, er0
	mov.l	@long_dst, er0
	cmp.l	er2, er0
	beq	.Lnext48
	fail
.Lnext48:
	mov.l	#0, er0
	mov.l	er0, @long_dst	; zero it again for the next use.

.if (sim_cpu == h8sx)
mov_l_reg32_to_disp2:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.l ers, @(dd:2, erd)
	mov.l	#long_dst-12, er1
	mov.l	er0, @(12:2, er1)	; Register plus 2-bit disp. operand
;;;	.word	0x0103
;;;	.word	0x6990

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	long_dst-12, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	er2, @long_dst
	beq	.Lnext52
	fail
.Lnext52:
	mov.l	#0, @long_dst	; zero it again for the next use.
.endif				; h8sx

mov_l_reg32_to_disp16:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.l ers, @(dd:16, erd)
	mov.l	#long_dst-4, er1
	mov.l	er0, @(4:16, er1)	; Register plus 16-bit disp. operand
;;;	.word	0x0100
;;;	.word	0x6f90
;;;	.word	0x0004

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32	long_dst-4, er1
	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	mov.l	#0, er0
	mov.l	@long_dst, er0
	cmp.l	er2, er0
	beq	.Lnext45
	fail
.Lnext45:
	mov.l	#0, er0
	mov.l	er0, @long_dst	; zero it again for the next use.

mov_l_reg32_to_disp32:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.l ers, @(dd:32, erd)
	mov.l	#long_dst-8, er1
	mov.l	er0, @(8:32, er1)	; Register plus 32-bit disp. operand
;;;	.word	0x7890
;;;	.word	0x6ba0
;;;	.long	8

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32	long_dst-8, er1
	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	mov.l	#0, er0
	mov.l	@long_dst, er0
	cmp.l	er2, er0
	beq	.Lnext46
	fail
.Lnext46:
	mov.l	#0, er0
	mov.l	er0, @long_dst	; zero it again for the next use.

mov_l_reg32_to_abs16:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.l ers, @aa:16
	mov.l	er0, @long_dst:16	; 16-bit address-direct operand
;;;	.word	0x0100
;;;	.word	0x6b80
;;;	.word	@long_dst

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
	test_gr_a5a5 1		; (first, because on h8/300 we must use one
	test_gr_a5a5 2		; to examine the destination memory).
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	mov.l	#0, er0
	mov.l	@long_dst, er0
	cmp.l	er0, er1
	beq	.Lnext41
	fail
.Lnext41:
	mov.l	#0, er0
	mov.l	er0, @long_dst	; zero it again for the next use.

mov_l_reg32_to_abs32:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.l ers, @aa:32
	mov.l	er0, @long_dst:32	; 32-bit address-direct operand
;;;	.word	0x0100
;;;	.word	0x6ba0
;;;	.long	@long_dst

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
	test_gr_a5a5 1		; (first, because on h8/300 we must use one
	test_gr_a5a5 2		; to examine the destination memory).
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	mov.l	#0, er0
	mov.l	@long_dst, er0
	cmp.l	er0, er1
	beq	.Lnext42
	fail
.Lnext42:
	mov.l	#0, er0
	mov.l	er0, @long_dst	; zero it again for the next use.

	;;
	;; Move long to register destination.
	;; 

mov_l_indirect_to_reg32:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.l @ers, erd
	mov.l	#long_src, er1
	mov.l	@er1, er0	; Register indirect operand
;;;	.word	0x0100
;;;	.word	0x6910

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32 0x77777777 er0

	test_h_gr32	long_src, er1
	test_gr_a5a5 2		; Make sure other general regs not disturbed
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

mov_l_postinc_to_reg32:		; post-increment from mem to register
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.l @ers+, erd

	mov.l	#long_src, er1
	mov.l	@er1+, er0	; Register post-incr operand
;;;	.word	0x0100
;;;	.word	0x6d10

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32 0x77777777 er0

	test_h_gr32	long_src+4, er1
	test_gr_a5a5 2		; Make sure other general regs not disturbed
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

.if (sim_cpu == h8sx)
mov_l_postdec_to_reg32:		; post-decrement from mem to register
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.l @ers-, erd

	mov.l	#long_src, er1
	mov.l	@er1-, er0	; Register post-decr operand
;;;	.word	0x0102
;;;	.word	0x6d10

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32 0x77777777 er0

	test_h_gr32	long_src-4, er1
	test_gr_a5a5 2		; Make sure other general regs not disturbed
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

mov_l_preinc_to_reg32:		; pre-increment from mem to register
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.l @+ers, erd

	mov.l	#long_src-4, er1
	mov.l	@+er1, er0	; Register pre-incr operand
;;;	.word	0x0101
;;;	.word	0x6d10

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32 0x77777777 er0

	test_h_gr32	long_src, er1
	test_gr_a5a5 2		; Make sure other general regs not disturbed
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

mov_l_predec_to_reg32:		; pre-decrement from mem to register
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.l @-ers, erd

	mov.l	#long_src+4, er1
	mov.l	@-er1, er0	; Register pre-decr operand
;;;	.word	0x0103
;;;	.word	0x6d10

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32 0x77777777 er0

	test_h_gr32	long_src, er1
	test_gr_a5a5 2		; Make sure other general regs not disturbed
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	
mov_l_disp2_to_reg32:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.l @(dd:2, ers), erd
	mov.l	#long_src-4, er1
	mov.l	@(4:2, er1), er0	; Register plus 2-bit disp. operand
;;; 	.word	0x0101
;;; 	.word	0x6910

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32 0x77777777 er0	; mov result:	a5a5 | 7777

	test_h_gr32	long_src-4, er1
	test_gr_a5a5 2		; Make sure other general regs not disturbed