movl.s

gdb-6.8 Linux下的调试程序 最新版本

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	long_dst, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	#0xdead, @long_dst
	beq	.Lnext14
	fail
.Lnext14:
	mov.l	#0, @long_dst	; zero it again for the next use.

mov_l_imm16_to_predec:		; pre-decrement from register to mem
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.l #xx:16, @-erd
	mov.l	#long_dst+4, er1
	mov.l	#0xdead:16, @-er1	; Imm16, register pre-decr operands
;;;	.word	0x7a7c
;;;	.word	0xdead
;;;	.word	0xb100

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	long_dst, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	#0xdead, @long_dst
	beq	.Lnext15
	fail
.Lnext15:
	mov.l	#0, @long_dst	; zero it again for the next use.

mov_l_imm16_to_disp2:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.l #xx:16, @(dd:2, erd)
	mov.l	#long_dst-12, er1
	mov.l	#0xdead:16, @(12:2, er1)	; Imm16, reg plus 2-bit disp. operand
;;;	.word	0x7a7c
;;;	.word	0xdead
;;;	.word	0x3100

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	long_dst-12, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	#0xdead, @long_dst
	beq	.Lnext16
	fail
.Lnext16:
	mov.l	#0, @long_dst	; zero it again for the next use.

mov_l_imm16_to_disp16:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.l #xx:16, @(dd:16, erd)
	mov.l	#long_dst-4, er1
	mov.l	#0xdead:16, @(4:16, er1)	; Register plus 16-bit disp. operand
;;;	.word	0x7a7c
;;;	.word	0xdead
;;;	.word	0xc100
;;;	.word	0x0004

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	long_dst-4, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	#0xdead, @long_dst
	beq	.Lnext17
	fail
.Lnext17:
	mov.l	#0, @long_dst	; zero it again for the next use.

mov_l_imm16_to_disp32:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.l #xx:16, @(dd:32, erd)
	mov.l	#long_dst-8, er1
	mov.l	#0xdead:16, @(8:32, er1)   ; Register plus 32-bit disp. operand
;;;	.word	0x7a7c
;;;	.word	0xdead
;;;	.word	0xc900
;;;	.long	8

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	long_dst-8, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	#0xdead, @long_dst
	beq	.Lnext18
	fail
.Lnext18:
	mov.l	#0, @long_dst	; zero it again for the next use.

mov_l_imm16_to_abs16:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.l #xx:16, @aa:16
	mov.l	#0xdead:16, @long_dst:16	; 16-bit address-direct operand
;;;	.word	0x7a7c
;;;	.word	0xdead
;;;	.word	0x4000
;;;	.word	@long_dst

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
	test_gr_a5a5 1		; (first, because on h8/300 we must use one
	test_gr_a5a5 2		; to examine the destination memory).
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	#0xdead, @long_dst
	beq	.Lnext19
	fail
.Lnext19:
	mov.l	#0, @long_dst	; zero it again for the next use.

mov_l_imm16_to_abs32:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.l #xx:16, @aa:32
	mov.l	#0xdead:16, @long_dst:32	; 32-bit address-direct operand
;;;	.word	0x7a7c
;;;	.word	0xdead
;;;	.word	0x4800
;;;	.long	@long_dst

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
	test_gr_a5a5 1		; (first, because on h8/300 we must use one
	test_gr_a5a5 2		; to examine the destination memory).
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	#0xdead, @long_dst
	beq	.Lnext20
	fail
.Lnext20:
	mov.l	#0, @long_dst	; zero it again for the next use.

mov_l_imm32_to_indirect:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.l #xx:32, @erd
	mov.l	#long_dst, er1
	mov.l	#0xcafedead:32, @er1	; Register indirect operand
;;;	.word	0x7a74
;;;	.long	0xcafedead
;;;	.word	0x0100

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	long_dst, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	#0xcafedead, @long_dst
	beq	.Lnext21
	fail
.Lnext21:
	mov.l	#0, @long_dst	; zero it again for the next use.

mov_l_imm32_to_postinc:		; post-increment from imm32 to mem
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.l #xx:32, @erd+
	mov.l	#long_dst, er1
	mov.l	#0xcafedead:32, @er1+	; Imm32, register post-incr operands.
;;;	.word	0x7a74
;;;	.long	0xcafedead
;;;	.word	0x8100

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	long_dst+4, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	#0xcafedead, @long_dst
	beq	.Lnext22
	fail
.Lnext22:
	mov.l	#0, @long_dst	; zero it again for the next use.

mov_l_imm32_to_postdec:		; post-decrement from imm32 to mem
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.l #xx:32, @erd-
	mov.l	#long_dst, er1
	mov.l	#0xcafedead:32, @er1-	; Imm32, register post-decr operands.
;;;	.word	0x7a74
;;;	.long	0xcafedead
;;;	.word	0xa100

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	long_dst-4, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	#0xcafedead, @long_dst
	beq	.Lnext23
	fail
.Lnext23:
	mov.l	#0, @long_dst	; zero it again for the next use.

mov_l_imm32_to_preinc:		; pre-increment from register to mem
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.l #xx:32, @+erd
	mov.l	#long_dst-4, er1
	mov.l	#0xcafedead:32, @+er1	; Imm32, register pre-incr operands
;;;	.word	0x7a74
;;;	.long	0xcafedead
;;;	.word	0x9100

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	long_dst, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	#0xcafedead, @long_dst
	beq	.Lnext24
	fail
.Lnext24:
	mov.l	#0, @long_dst	; zero it again for the next use.

mov_l_imm32_to_predec:		; pre-decrement from register to mem
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.l #xx:32, @-erd
	mov.l	#long_dst+4, er1
	mov.l	#0xcafedead:32, @-er1	; Imm32, register pre-decr operands
;;;	.word	0x7a74
;;;	.long	0xcafedead
;;;	.word	0xb100

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	long_dst, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	#0xcafedead, @long_dst
	beq	.Lnext25
	fail
.Lnext25:
	mov.l	#0, @long_dst	; zero it again for the next use.

mov_l_imm32_to_disp2:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.l #xx:32, @(dd:2, erd)
	mov.l	#long_dst-12, er1
	mov.l	#0xcafedead:32, @(12:2, er1)	; Imm32, reg plus 2-bit disp. operand
;;;	.word	0x7a74
;;;	.long	0xcafedead
;;;	.word	0x3100

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	long_dst-12, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	#0xcafedead, @long_dst
	beq	.Lnext26
	fail
.Lnext26:
	mov.l	#0, @long_dst	; zero it again for the next use.

mov_l_imm32_to_disp16:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.l #xx:32, @(dd:16, erd)
	mov.l	#long_dst-4, er1
	mov.l	#0xcafedead:32, @(4:16, er1)	; Register plus 16-bit disp. operand
;;;	.word	0x7a74
;;;	.long	0xcafedead
;;;	.word	0xc100
;;;	.word	0x0004

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	long_dst-4, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	#0xcafedead, @long_dst
	beq	.Lnext27
	fail
.Lnext27:
	mov.l	#0, @long_dst	; zero it again for the next use.

mov_l_imm32_to_disp32:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.l #xx:32, @(dd:32, erd)
	mov.l	#long_dst-8, er1
	mov.l	#0xcafedead:32, @(8:32, er1)   ; Register plus 32-bit disp. operand
;;;	.word	0x7a74
;;;	.long	0xcafedead
;;;	.word	0xc900
;;;	.long	8

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	long_dst-8, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	#0xcafedead, @long_dst
	beq	.Lnext28
	fail
.Lnext28:
	mov.l	#0, @long_dst	; zero it again for the next use.

mov_l_imm32_to_abs16:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.l #xx:32, @aa:16
	mov.l	#0xcafedead:32, @long_dst:16	; 16-bit address-direct operand
;;;	.word	0x7a74
;;;	.long	0xcafedead
;;;	.word	0x4000
;;;	.word	@long_dst

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
	test_gr_a5a5 1		; (first, because on h8/300 we must use one
	test_gr_a5a5 2		; to examine the destination memory).
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	#0xcafedead, @long_dst
	beq	.Lnext29
	fail
.Lnext29:
	mov.l	#0, @long_dst	; zero it again for the next use.

mov_l_imm32_to_abs32:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;;  mov.l #xx:32, @aa:32
	mov.l	#0xcafedead:32, @long_dst:32	; 32-bit address-direct operand
;;;	.word	0x7a74
;;;	.long	0xcafedead
;;;	.word	0x4800
;;;	.long	@long_dst

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
	test_gr_a5a5 1		; (first, because on h8/300 we must use one
	test_gr_a5a5 2		; to examine the destination memory).
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7