📄 shlr.s
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test_neg_clear test_h_gr32 word_dest er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 cmp.w #0x0a5a, @word_dest beq .Lwpredec4 fail.Lwpredec4: mov.w #0xa5a5, @word_destshlr_w_disp2_4: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest-4, er0 shlr.w #4, @(4:2, er0) ; shift right logical by four, disp2;;; .word 0x0156;;; .word 0x6908;;; .word 0x1120 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 word_dest-4 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 cmp.w #0x0a5a, @word_dest beq .Lwdisp24 fail.Lwdisp24: mov.w #0xa5a5, @word_destshlr_w_disp16_4: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest-44, er0 shlr.w #4, @(44:16, er0) ; shift right logical by four, disp16;;; .word 0x0154;;; .word 0x6f08;;; .word 44;;; .word 0x1120 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 word_dest-44 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 cmp.w #0x0a5a, @word_dest beq .Lwdisp164 fail.Lwdisp164: mov.w #0xa5a5, @word_destshlr_w_disp32_4: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest-666, er0 shlr.w #4, @(666:32, er0) ; shift right logical by four, disp32;;; .word 0x7884;;; .word 0x6b28;;; .long 666;;; .word 0x1120 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 word_dest-666 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 cmp.w #0x0a5a, @word_dest beq .Lwdisp324 fail.Lwdisp324: mov.w #0xa5a5, @word_destshlr_w_abs16_4: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero shlr.w #4, @word_dest:16 ; shift right logical by four, abs16;;; .word 0x6b18;;; .word word_dest;;; .word 0x1120 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_gr_a5a5 0 ; Make sure ALL general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 cmp.w #0x0a5a, @word_dest beq .Lwabs164 fail.Lwabs164: mov.w #0xa5a5, @word_destshlr_w_abs32_4: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero shlr.w #4, @word_dest:32 ; shift right logical by four, abs32;;; .word 0x6b38;;; .long word_dest;;; .word 0x1120 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_gr_a5a5 0 ; Make sure ALL general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 cmp.w #0x0a5a, @word_dest beq .Lwabs324 fail.Lwabs324: mov.w #0xa5a5, @word_destshlr_w_reg16_8: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero shlr.w #8, r0 ; shift right logical by eight;;; .word 0x1160 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr16 0x00a5 r0 ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 test_h_gr32 0xa5a500a5 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7shlr_w_ind_8: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest, er0 shlr.w #8, @er0 ; shift right logical by eight, indirect;;; .word 0x7d80;;; .word 0x1160 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 word_dest er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 cmp.w #0x00a5, @word_dest beq .Lwind8 fail.Lwind8: mov.w #0xa5a5, @word_destshlr_w_postinc_8: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest, er0 shlr.w #8, @er0+ ; shift right logical by eight, postinc;;; .word 0x0154;;; .word 0x6d08;;; .word 0x1160 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 word_dest+2 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 cmp.w #0x00a5, @word_dest beq .Lwpostinc8 fail.Lwpostinc8: mov.w #0xa5a5, @word_destshlr_w_postdec_8: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest, er0 shlr.w #8, @er0- ; shift right logical by eight, postdec;;; .word 0x0156;;; .word 0x6d08;;; .word 0x1160 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 word_dest-2 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 cmp.w #0x00a5, @word_dest beq .Lwpostdec8 fail.Lwpostdec8: mov.w #0xa5a5, @word_destshlr_w_preinc_8: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest-2, er0 shlr.w #8, @+er0 ; shift right logical by eight, preinc;;; .word 0x0155;;; .word 0x6d08;;; .word 0x1160 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 word_dest er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 cmp.w #0x00a5, @word_dest beq .Lwpreinc8 fail.Lwpreinc8: mov.w #0xa5a5, @word_destshlr_w_predec_8: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest+2, er0 shlr.w #8, @-er0 ; shift right logical by eight, predec;;; .word 0x0157;;; .word 0x6d08;;; .word 0x1160 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 word_dest er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 cmp.w #0x00a5, @word_dest beq .Lwpredec8 fail.Lwpredec8: mov.w #0xa5a5, @word_destshlr_w_disp2_8: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest-4, er0 shlr.w #8, @(4:2, er0) ; shift right logical by eight, disp2;;; .word 0x0156;;; .word 0x6908;;; .word 0x1160 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 word_dest-4 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 cmp.w #0x00a5, @word_dest beq .Lwdisp28 fail.Lwdisp28: mov.w #0xa5a5, @word_destshlr_w_disp16_8: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest-44, er0 shlr.w #8, @(44:16, er0) ; shift right logical by eight, disp16;;; .word 0x0154;;; .word 0x6f08;;; .word 44;;; .word 0x1160 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 word_dest-44 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 cmp.w #0x00a5, @word_dest beq .Lwdisp168 fail.Lwdisp168: mov.w #0xa5a5, @word_destshlr_w_disp32_8: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest-666, er0 shlr.w #8, @(666:32, er0) ; shift right logical by eight, disp32;;; .word 0x7884;;; .word 0x6b28;;; .long 666;;; .word 0x1160 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 word_dest-666 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 cmp.w #0x00a5, @word_dest beq .Lwdisp328 fail.Lwdisp328: mov.w #0xa5a5, @word_destshlr_w_abs16_8: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero shlr.w #8, @word_dest:16 ; shift right logical by eight, abs16;;; .word 0x6b18;;; .word word_dest;;; .word 0x1160 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_gr_a5a5 0 ; Make sure ALL general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 cmp.w #0x00a5, @word_dest beq .Lwabs168 fail.Lwabs168: mov.w #0xa5a5, @word_destshlr_w_abs32_8: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero shlr.w #8, @word_dest:32 ; shift right logical by eight, abs32;;; .word 0x6b38;;; .long word_dest;;; .word 0x1160 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_gr_a5a5 0 ; Make sure ALL general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 cmp.w #0x00a5, @word_dest beq .Lwabs328 fail.Lwabs328: mov.w #0xa5a5, @word_destshlr_l_imm5_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero shlr.l #31:5, er0 ; shift right logical by 5-bit immediate;;; .word 0x0399;;; .word 0x1130 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear ; 1010 0101 1010 0101 1010 0101 1010 0101 ; -> 0000 0000 0000 0000 0000 0000 0000 0001 test_h_gr32 0x1 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7.endifshlr_l_reg32_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero shlr.l er0 ; shift right logical by one, register;;; .word 0x1130 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear ; 1010 0101 1010 0101 1010 0101 1010 0101 ; -> 0101 0010 1101 0010 1101 0010 1101 0010 test_h_gr32 0x52d2d2d2 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7.if (sim_cpu == h8sx)shlr_l_ind_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #long_dest, er0 shlr.l @er0 ; shift right logical by one, indirect;;; .word 0x0104;;; .word 0x6908;;; .word 0x1130 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 long_dest er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 1010 0101 1010 0101 ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 cmp.l #0x52d2d2d2, @long_dest beq .Llind1 fail.Llind1: mov #0xa5a5a5a5, @long_destshlr_l_postinc_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #long_dest, er0 shlr.l @er0+ ; shift right logical by one, postinc;;; .word 0x0104;;; .word 0x6d08;;; .word 0x1130 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 long_dest+4 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 1010 0101 1010 0101 ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 cmp.l #0x52d2d2d2, @long_dest beq .Llpostinc1 fail.Llpostinc1: mov #0xa5a5a5a5, @long_destshlr_l_postdec_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #long_dest, er0 shlr.l @er0- ; shift right logical by one, postdec;;; .word 0x0106;;; .word 0x6d08;;; .word 0x1130 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 long_dest-4 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4⌨️ 快捷键说明
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