📄 shlr.s
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mov.w #0xa5a5, @word_destshlr_w_disp16_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest-44, er0 shlr.w @(44:16, er0) ; shift right logical by one, disp16;;; .word 0x0154;;; .word 0x6f08;;; .word 44;;; .word 0x1110 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 word_dest-44 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 cmp.w #0x52d2, @word_dest beq .Lwdisp161 fail.Lwdisp161: mov.w #0xa5a5, @word_destshlr_w_disp32_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest-666, er0 shlr.w @(666:32, er0) ; shift right logical by one, disp32;;; .word 0x7884;;; .word 0x6b28;;; .long 666;;; .word 0x1110 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 word_dest-666 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 cmp.w #0x52d2, @word_dest beq .Lwdisp321 fail.Lwdisp321: mov.w #0xa5a5, @word_destshlr_w_abs16_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero shlr.w @word_dest:16 ; shift right logical by one, abs16;;; .word 0x6b18;;; .word word_dest;;; .word 0x1110 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_gr_a5a5 0 ; Make sure ALL general regs not disturbed test_gr_a5a5 1 test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 cmp.w #0x52d2, @word_dest beq .Lwabs161 fail.Lwabs161: mov.w #0xa5a5, @word_destshlr_w_abs32_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero shlr.w @word_dest:32 ; shift right logical by one, abs32;;; .word 0x6b38;;; .long word_dest;;; .word 0x1110 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_gr_a5a5 0 ; Make sure ALL general regs not disturbed test_gr_a5a5 1 test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 cmp.w #0x52d2, @word_dest beq .Lwabs321 fail.Lwabs321: mov.w #0xa5a5, @word_dest.endif shlr_w_reg16_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero shlr.w #2, r0 ; shift right logical by two;;; .word 0x1150 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr16 0x2969 r0 ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 test_h_gr32 0xa5a52969 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7.if (sim_cpu == h8sx)shlr_w_ind_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest, er0 shlr.w #2, @er0 ; shift right logical by two, indirect;;; .word 0x7d80;;; .word 0x1150 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 word_dest er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 cmp.w #0x2969, @word_dest beq .Lwind2 fail.Lwind2: mov.w #0xa5a5, @word_destshlr_w_postinc_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest, er0 shlr.w #2, @er0+ ; shift right logical by two, postinc;;; .word 0x0154;;; .word 0x6d08;;; .word 0x1150 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 word_dest+2 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 cmp.w #0x2969, @word_dest beq .Lwpostinc2 fail.Lwpostinc2: mov.w #0xa5a5, @word_destshlr_w_postdec_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest, er0 shlr.w #2, @er0- ; shift right logical by two, postdec;;; .word 0x0156;;; .word 0x6d08;;; .word 0x1150 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 word_dest-2 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 cmp.w #0x2969, @word_dest beq .Lwpostdec2 fail.Lwpostdec2: mov.w #0xa5a5, @word_destshlr_w_preinc_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest-2, er0 shlr.w #2, @+er0 ; shift right logical by two, preinc;;; .word 0x0155;;; .word 0x6d08;;; .word 0x1150 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 word_dest er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 cmp.w #0x2969, @word_dest beq .Lwpreinc2 fail.Lwpreinc2: mov.w #0xa5a5, @word_destshlr_w_predec_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest+2, er0 shlr.w #2, @-er0 ; shift right logical by two, predec;;; .word 0x0157;;; .word 0x6d08;;; .word 0x1150 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 word_dest er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 cmp.w #0x2969, @word_dest beq .Lwpredec2 fail.Lwpredec2: mov.w #0xa5a5, @word_destshlr_w_disp2_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest-4, er0 shlr.w #2, @(4:2, er0) ; shift right logical by two, disp2;;; .word 0x0156;;; .word 0x6908;;; .word 0x1150 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 word_dest-4 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 cmp.w #0x2969, @word_dest beq .Lwdisp22 fail.Lwdisp22: mov.w #0xa5a5, @word_destshlr_w_disp16_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest-44, er0 shlr.w #2, @(44:16, er0) ; shift right logical by two, disp16;;; .word 0x0154;;; .word 0x6f08;;; .word 44;;; .word 0x1150 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 word_dest-44 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 cmp.w #0x2969, @word_dest beq .Lwdisp162 fail.Lwdisp162: mov.w #0xa5a5, @word_destshlr_w_disp32_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest-666, er0 shlr.w #2, @(666:32, er0) ; shift right logical by two, disp32;;; .word 0x7884;;; .word 0x6b28;;; .long 666;;; .word 0x1150 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 word_dest-666 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 cmp.w #0x2969, @word_dest beq .Lwdisp322 fail.Lwdisp322: mov.w #0xa5a5, @word_destshlr_w_abs16_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero shlr.w #2, @word_dest:16 ; shift right logical by two, abs16;;; .word 0x6b18;;; .word word_dest;;; .word 0x1150 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_gr_a5a5 0 ; Make sure ALL general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 cmp.w #0x2969, @word_dest beq .Lwabs162 fail.Lwabs162: mov.w #0xa5a5, @word_destshlr_w_abs32_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero shlr.w #2, @word_dest:32 ; shift right logical by two, abs32;;; .word 0x6b38;;; .long word_dest;;; .word 0x1150 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_gr_a5a5 0 ; Make sure ALL general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 cmp.w #0x2969, @word_dest beq .Lwabs322 fail.Lwabs322: mov.w #0xa5a5, @word_dest shlr_w_reg16_4: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero shlr.w #4, r0 ; shift right logical by four;;; .word 0x1120 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr16 0x0a5a r0 ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 test_h_gr32 0xa5a50a5a er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7shlr_w_reg16_reg8: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #5, r1l shlr.w r1l, r0 ; shift right logical by register value test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr16 0x052d r0 ; 1010 0101 1010 0101 -> 0000 0101 0010 1101 test_h_gr32 0xa5a5052d er0 test_h_gr32 0xa5a5a505 er1 test_gr_a5a5 2 ; Make sure other general regs not disturbed test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7shlr_w_ind_4: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest, er0 shlr.w #4, @er0 ; shift right logical by four, indirect;;; .word 0x7d80;;; .word 0x1120 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 word_dest er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 cmp.w #0x0a5a, @word_dest beq .Lwind4 fail.Lwind4: mov.w #0xa5a5, @word_destshlr_w_postinc_4: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest, er0 shlr.w #4, @er0+ ; shift right logical by four, postinc;;; .word 0x0154;;; .word 0x6d08;;; .word 0x1120 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 word_dest+2 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 cmp.w #0x0a5a, @word_dest beq .Lwpostinc4 fail.Lwpostinc4: mov.w #0xa5a5, @word_destshlr_w_postdec_4: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest, er0 shlr.w #4, @er0- ; shift right logical by four, postdec;;; .word 0x0156;;; .word 0x6d08;;; .word 0x1120 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 word_dest-2 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 cmp.w #0x0a5a, @word_dest beq .Lwpostdec4 fail.Lwpostdec4: mov.w #0xa5a5, @word_destshlr_w_preinc_4: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest-2, er0 shlr.w #4, @+er0 ; shift right logical by four, preinc;;; .word 0x0155;;; .word 0x6d08;;; .word 0x1120 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 word_dest er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 cmp.w #0x0a5a, @word_dest beq .Lwpreinc4 fail.Lwpreinc4: mov.w #0xa5a5, @word_destshlr_w_predec_4: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest+2, er0 shlr.w #4, @-er0 ; shift right logical by four, predec;;; .word 0x0157;;; .word 0x6d08;;; .word 0x1120 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear⌨️ 快捷键说明
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