📄 shlr.s
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_gr_a5a5 0 ; Make sure ALL general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0010 1001 cmp.b #0x29, @byte_dest beq .Lbabs162 fail.Lbabs162: mov.b #0xa5, @byte_destshlr_b_abs32_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero shlr.b #2, @byte_dest:32 ; shift right logical by two, abs32;;; .word 0x6a38;;; .long byte_dest;;; .word 0x1140 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_gr_a5a5 0 ; Make sure ALL general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0010 1001 cmp.b #0x29, @byte_dest beq .Lbabs322 fail.Lbabs322: mov.b #0xa5, @byte_destshlr_b_reg8_4: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero shlr.b #4, r0l ; shift right logical by four;;; .word 0x11a8 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr16 0xa50a r0 ; 1010 0101 -> 0000 1010 test_h_gr32 0xa5a5a50a er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7shlr_b_reg8_reg8: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #5, r0h shlr.b r0h, r0l ; shift right logical by register value test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr16 0x0505 r0 ; 1010 0101 -> 0000 0101 test_h_gr32 0xa5a50505 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7shlr_b_ind_4: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #byte_dest, er0 shlr.b #4, @er0 ; shift right logical by four, indirect;;; .word 0x7d00;;; .word 0x11a0 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 byte_dest er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0000 1010 cmp.b #0x0a, @byte_dest beq .Lbind4 fail.Lbind4: mov.b #0xa5, @byte_destshlr_b_postinc_4: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #byte_dest, er0 shlr.b #4, @er0+ ; shift right logical by four, postinc;;; .word 0x0174;;; .word 0x6c08;;; .word 0x11a0 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 byte_dest+1 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0000 1010 cmp.b #0x0a, @byte_dest beq .Lbpostinc4 fail.Lbpostinc4: mov.b #0xa5, @byte_destshlr_b_postdec_4: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #byte_dest, er0 shlr.b #4, @er0- ; shift right logical by four, postdec;;; .word 0x0176;;; .word 0x6c08;;; .word 0x11a0 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 byte_dest-1 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0000 1010 cmp.b #0x0a, @byte_dest beq .Lbpostdec4 fail.Lbpostdec4: mov.b #0xa5, @byte_destshlr_b_preinc_4: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #byte_dest-1, er0 shlr.b #4, @+er0 ; shift right logical by four, preinc;;; .word 0x0175;;; .word 0x6c08;;; .word 0x11a0 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 byte_dest er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0000 1010 cmp.b #0x0a, @byte_dest beq .Lbpreinc4 fail.Lbpreinc4: mov.b #0xa5, @byte_destshlr_b_predec_4: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #byte_dest+1, er0 shlr.b #4, @-er0 ; shift right logical by four, predec;;; .word 0x0177;;; .word 0x6c08;;; .word 0x11a0 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 byte_dest er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0000 1010 cmp.b #0x0a, @byte_dest beq .Lbpredec4 fail.Lbpredec4: mov.b #0xa5, @byte_destshlr_b_disp2_4: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #byte_dest-2, er0 shlr.b #4, @(2:2, er0) ; shift right logical by four, disp2;;; .word 0x0176;;; .word 0x6808;;; .word 0x11a0 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 byte_dest-2 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0000 1010 cmp.b #0x0a, @byte_dest beq .Lbdisp24 fail.Lbdisp24: mov.b #0xa5, @byte_destshlr_b_disp16_4: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #byte_dest-44, er0 shlr.b #4, @(44:16, er0) ; shift right logical by four, disp16;;; .word 0x0174;;; .word 0x6e08;;; .word 44;;; .word 0x11a0 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 byte_dest-44 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0000 1010 cmp.b #0x0a, @byte_dest beq .Lbdisp164 fail.Lbdisp164: mov.b #0xa5, @byte_destshlr_b_disp32_4: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #byte_dest-666, er0 shlr.b #4, @(666:32, er0) ; shift right logical by four, disp32;;; .word 0x7884;;; .word 0x6a28;;; .long 666;;; .word 0x11a0 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 byte_dest-666 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0000 1010 cmp.b #0x0a, @byte_dest beq .Lbdisp324 fail.Lbdisp324: mov.b #0xa5, @byte_destshlr_b_abs16_4: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero shlr.b #4, @byte_dest:16 ; shift right logical by four, abs16;;; .word 0x6a18;;; .word byte_dest;;; .word 0x11a0 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_gr_a5a5 0 ; Make sure ALL general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0000 1010 cmp.b #0x0a, @byte_dest beq .Lbabs164 fail.Lbabs164: mov.b #0xa5, @byte_destshlr_b_abs32_4: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero shlr.b #4, @byte_dest:32 ; shift right logical by four, abs32;;; .word 0x6a38;;; .long byte_dest;;; .word 0x11a0 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_gr_a5a5 0 ; Make sure ALL general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0000 1010 cmp.b #0x0a, @byte_dest beq .Lbabs324 fail.Lbabs324: mov.b #0xa5, @byte_dest.endif.if (sim_cpu == h8sx)shlr_w_imm5_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero shlr.w #15:5, r0 ; shift right logical by 5-bit immediate;;; .word 0x038f;;; .word 0x1110 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear ; 1010 0101 1010 0101 -> 0000 0000 0000 0001 test_h_gr32 0xa5a50001 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7.endif.if (sim_cpu) ; Not available in h8300 modeshlr_w_reg16_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero shlr.w r0 ; shift right logical by one;;; .word 0x1110 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr16 0x52d2 r0 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 test_h_gr32 0xa5a552d2 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7.if (sim_cpu == h8sx)shlr_w_ind_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest, er0 shlr.w @er0 ; shift right logical by one, indirect;;; .word 0x7d80;;; .word 0x1110 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 word_dest er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 cmp.w #0x52d2, @word_dest beq .Lwind1 fail.Lwind1: mov.w #0xa5a5, @word_destshlr_w_postinc_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest, er0 shlr.w @er0+ ; shift right logical by one, postinc;;; .word 0x0154;;; .word 0x6d08;;; .word 0x1110 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 word_dest+2 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 cmp.w #0x52d2, @word_dest beq .Lwpostinc1 fail.Lwpostinc1: mov.w #0xa5a5, @word_destshlr_w_postdec_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest, er0 shlr.w @er0- ; shift right logical by one, postdec;;; .word 0x0156;;; .word 0x6d08;;; .word 0x1110 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 word_dest-2 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 cmp.w #0x52d2, @word_dest beq .Lwpostdec1 fail.Lwpostdec1: mov.w #0xa5a5, @word_destshlr_w_preinc_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest-2, er0 shlr.w @+er0 ; shift right logical by one, preinc;;; .word 0x0155;;; .word 0x6d08;;; .word 0x1110 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 word_dest er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 cmp.w #0x52d2, @word_dest beq .Lwpreinc1 fail.Lwpreinc1: mov.w #0xa5a5, @word_destshlr_w_predec_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest+2, er0 shlr.w @-er0 ; shift right logical by one, predec;;; .word 0x0157;;; .word 0x6d08;;; .word 0x1110 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 word_dest er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 cmp.w #0x52d2, @word_dest beq .Lwpredec1 fail.Lwpredec1: mov.w #0xa5a5, @word_destshlr_w_disp2_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest-4, er0 shlr.w @(4:2, er0) ; shift right logical by one, disp2;;; .word 0x0156;;; .word 0x6908;;; .word 0x1110 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 word_dest-4 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 cmp.w #0x52d2, @word_dest beq .Lwdisp21 fail.Lwdisp21:⌨️ 快捷键说明
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