📄 shlr.s
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# Hitachi H8 testcase 'shlr'# mach(): all# as(h8300): --defsym sim_cpu=0# as(h8300h): --defsym sim_cpu=1# as(h8300s): --defsym sim_cpu=2# as(h8sx): --defsym sim_cpu=3# ld(h8300h): -m h8300helf# ld(h8300s): -m h8300self# ld(h8sx): -m h8300sxelf .include "testutils.inc" start .databyte_dest: .byte 0xa5 .align 2word_dest: .word 0xa5a5 .align 4long_dest: .long 0xa5a5a5a5 .textshlr_b_reg8_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero shlr.b r0l ; shift right logical by one;;; .word 0x1108 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr16 0xa552 r0 ; 1010 0101 -> 0101 0010.if (sim_cpu) test_h_gr32 0xa5a5a552 er0.endif test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7.if (sim_cpu == h8sx)shlr_b_ind_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #byte_dest, er0 shlr.b @er0 ; shift right logical by one, indirect;;; .word 0x7d00;;; .word 0x1100 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 byte_dest er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0101 0010 cmp.b #0x52, @byte_dest beq .Lbind1 fail.Lbind1: mov.b #0xa5, @byte_destshlr_b_postinc_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #byte_dest, er0 shlr.b @er0+ ; shift right logical by one, postinc;;; .word 0x0174;;; .word 0x6c08;;; .word 0x1100 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 byte_dest+1 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0101 0010 cmp.b #0x52, @byte_dest beq .Lbpostinc1 fail.Lbpostinc1: mov.b #0xa5, @byte_destshlr_b_postdec_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #byte_dest, er0 shlr.b @er0- ; shift right logical by one, postdec;;; .word 0x0176;;; .word 0x6c08;;; .word 0x1100 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 byte_dest-1 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0101 0010 cmp.b #0x52, @byte_dest beq .Lbpostdec1 fail.Lbpostdec1: mov.b #0xa5, @byte_destshlr_b_preinc_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #byte_dest-1, er0 shlr.b @+er0 ; shift right logical by one, preinc;;; .word 0x0175;;; .word 0x6c08;;; .word 0x1100 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 byte_dest er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0101 0010 cmp.b #0x52, @byte_dest beq .Lbpreinc1 fail.Lbpreinc1: mov.b #0xa5, @byte_destshlr_b_predec_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #byte_dest+1, er0 shlr.b @-er0 ; shift right logical by one, predec;;; .word 0x0177;;; .word 0x6c08;;; .word 0x1100 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 byte_dest er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0101 0010 cmp.b #0x52, @byte_dest beq .Lbpredec1 fail.Lbpredec1: mov.b #0xa5, @byte_destshlr_b_disp2_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #byte_dest-2, er0 shlr.b @(2:2, er0) ; shift right logical by one, disp2;;; .word 0x0176;;; .word 0x6808;;; .word 0x1100 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 byte_dest-2 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0101 0010 cmp.b #0x52, @byte_dest beq .Lbdisp21 fail.Lbdisp21: mov.b #0xa5, @byte_destshlr_b_disp16_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #byte_dest-44, er0 shlr.b @(44:16, er0) ; shift right logical by one, disp16;;; .word 0x0174;;; .word 0x6e08;;; .word 44;;; .word 0x1100 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 byte_dest-44 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0101 0010 cmp.b #0x52, @byte_dest beq .Lbdisp161 fail.Lbdisp161: mov.b #0xa5, @byte_destshlr_b_disp32_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #byte_dest-666, er0 shlr.b @(666:32, er0) ; shift right logical by one, disp32;;; .word 0x7884;;; .word 0x6a28;;; .long 666;;; .word 0x1100 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 byte_dest-666 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0101 0010 cmp.b #0x52, @byte_dest beq .Lbdisp321 fail.Lbdisp321: mov.b #0xa5, @byte_destshlr_b_abs16_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero shlr.b @byte_dest:16 ; shift right logical by one, abs16;;; .word 0x6a18;;; .word byte_dest;;; .word 0x1100 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_gr_a5a5 0 ; Make sure ALL general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0101 0010 cmp.b #0x52, @byte_dest beq .Lbabs161 fail.Lbabs161: mov.b #0xa5, @byte_destshlr_b_abs32_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero shlr.b @byte_dest:32 ; shift right logical by one, abs32;;; .word 0x6a38;;; .long byte_dest;;; .word 0x1100 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_gr_a5a5 0 ; Make sure ALL general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0101 0010 cmp.b #0x52, @byte_dest beq .Lbabs321 fail.Lbabs321: mov.b #0xa5, @byte_dest.endifshlr_b_reg8_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero shlr.b #2, r0l ; shift right logical by two;;; .word 0x1148 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr16 0xa529 r0 ; 1010 0101 -> 0010 1001.if (sim_cpu) test_h_gr32 0xa5a5a529 er0.endif test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7.if (sim_cpu == h8sx)shlr_b_ind_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #byte_dest, er0 shlr.b #2, @er0 ; shift right logical by two, indirect;;; .word 0x7d00;;; .word 0x1140 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 byte_dest er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0010 1001 cmp.b #0x29, @byte_dest beq .Lbind2 fail.Lbind2: mov.b #0xa5, @byte_destshlr_b_postinc_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #byte_dest, er0 shlr.b #2, @er0+ ; shift right logical by two, postinc;;; .word 0x0174;;; .word 0x6c08;;; .word 0x1140 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 byte_dest+1 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0010 1001 cmp.b #0x29, @byte_dest beq .Lbpostinc2 fail.Lbpostinc2: mov.b #0xa5, @byte_destshlr_b_postdec_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #byte_dest, er0 shlr.b #2, @er0- ; shift right logical by two, postdec;;; .word 0x0176;;; .word 0x6c08;;; .word 0x1140 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 byte_dest-1 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0010 1001 cmp.b #0x29, @byte_dest beq .Lbpostdec2 fail.Lbpostdec2: mov.b #0xa5, @byte_destshlr_b_preinc_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #byte_dest-1, er0 shlr.b #2, @+er0 ; shift right logical by two, preinc;;; .word 0x0175;;; .word 0x6c08;;; .word 0x1140 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 byte_dest er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0010 1001 cmp.b #0x29, @byte_dest beq .Lbpreinc2 fail.Lbpreinc2: mov.b #0xa5, @byte_destshlr_b_predec_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #byte_dest+1, er0 shlr.b #2, @-er0 ; shift right logical by two, predec;;; .word 0x0177;;; .word 0x6c08;;; .word 0x1140 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 byte_dest er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0010 1001 cmp.b #0x29, @byte_dest beq .Lbpredec2 fail.Lbpredec2: mov.b #0xa5, @byte_destshlr_b_disp2_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #byte_dest-2, er0 shlr.b #2, @(2:2, er0) ; shift right logical by two, disp2;;; .word 0x0176;;; .word 0x6808;;; .word 0x1140 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 byte_dest-2 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0010 1001 cmp.b #0x29, @byte_dest beq .Lbdisp22 fail.Lbdisp22: mov.b #0xa5, @byte_destshlr_b_disp16_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #byte_dest-44, er0 shlr.b #2, @(44:16, er0) ; shift right logical by two, disp16;;; .word 0x0174;;; .word 0x6e08;;; .word 44;;; .word 0x1140 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 byte_dest-44 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0010 1001 cmp.b #0x29, @byte_dest beq .Lbdisp162 fail.Lbdisp162: mov.b #0xa5, @byte_destshlr_b_disp32_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #byte_dest-666, er0 shlr.b #2, @(666:32, er0) ; shift right logical by two, disp32;;; .word 0x7884;;; .word 0x6a28;;; .long 666;;; .word 0x1140 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 byte_dest-666 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0010 1001 cmp.b #0x29, @byte_dest beq .Lbdisp322 fail.Lbdisp322: mov.b #0xa5, @byte_destshlr_b_abs16_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero shlr.b #2, @byte_dest:16 ; shift right logical by two, abs16;;; .word 0x6a18;;; .word byte_dest;;; .word 0x1140⌨️ 快捷键说明
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