📄 rotr.s

📁 gdb-6.8 Linux下的调试程序最新版本
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	; 1010 0101 1010 0101 1010 0101 1010 0101 	; -> 1101 0010 1101 0010 1101 0010 1101 0010	test_h_gr32  0xd2d2d2d2 er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7.if (sim_cpu == h8sx)rotr_l_ind_1:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	mov	#long_dest, er0	rotr.l	@er0	; shift right arithmetic by one, indirect	test_carry_set		; H=0 N=1 Z=0 V=0 C=1	test_zero_clear	test_ovf_clear	test_neg_set	test_h_gr32  long_dest er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 1010 0101 1010 0101	;; -> 1101 0010 1101 0010 1101 0010 1101 0010	cmp.l	#0xd2d2d2d2, @long_dest	beq	.Llind1	fail.Llind1:	mov	#0xa5a5a5a5, @long_destrotr_l_postinc_1:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	mov	#long_dest, er0	rotr.l	@er0+	; shift right arithmetic by one, postinc	test_carry_set		; H=0 N=1 Z=0 V=0 C=1	test_zero_clear	test_ovf_clear	test_neg_set	test_h_gr32  long_dest+4 er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 1010 0101 1010 0101	;; -> 1101 0010 1101 0010 1101 0010 1101 0010	cmp.l	#0xd2d2d2d2, @long_dest	beq	.Llpostinc1	fail.Llpostinc1:	mov	#0xa5a5a5a5, @long_destrotr_l_postdec_1:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	mov	#long_dest, er0	rotr.l	@er0-	; shift right arithmetic by one, postdec	test_carry_set		; H=0 N=1 Z=0 V=0 C=1	test_zero_clear	test_ovf_clear	test_neg_set	test_h_gr32  long_dest-4 er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 1010 0101 1010 0101	;; -> 1101 0010 1101 0010 1101 0010 1101 0010	cmp.l	#0xd2d2d2d2, @long_dest	beq	.Llpostdec1	fail.Llpostdec1:	mov	#0xa5a5a5a5, @long_destrotr_l_preinc_1:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	mov	#long_dest-4, er0	rotr.l	@+er0	; shift right arithmetic by one, preinc	test_carry_set		; H=0 N=1 Z=0 V=0 C=1	test_zero_clear	test_ovf_clear	test_neg_set	test_h_gr32  long_dest er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 1010 0101 1010 0101	;; -> 1101 0010 1101 0010 1101 0010 1101 0010	cmp.l	#0xd2d2d2d2, @long_dest	beq	.Llpreinc1	fail.Llpreinc1:	mov	#0xa5a5a5a5, @long_destrotr_l_predec_1:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	mov	#long_dest+4, er0	rotr.l	@-er0	; shift right arithmetic by one, predec	test_carry_set		; H=0 N=1 Z=0 V=0 C=1	test_zero_clear	test_ovf_clear	test_neg_set	test_h_gr32  long_dest er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 1010 0101 1010 0101	;; -> 1101 0010 1101 0010 1101 0010 1101 0010	cmp.l	#0xd2d2d2d2, @long_dest	beq	.Llpredec1	fail.Llpredec1:	mov	#0xa5a5a5a5, @long_destrotr_l_disp2_1:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	mov	#long_dest-8, er0	rotr.l	@(8:2, er0)	; shift right arithmetic by one, disp2	test_carry_set		; H=0 N=1 Z=0 V=0 C=1	test_zero_clear	test_ovf_clear	test_neg_set	test_h_gr32  long_dest-8 er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 1010 0101 1010 0101	;; -> 1101 0010 1101 0010 1101 0010 1101 0010	cmp.l	#0xd2d2d2d2, @long_dest	beq	.Lldisp21	fail.Lldisp21:	mov	#0xa5a5a5a5, @long_destrotr_l_disp16_1:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	mov	#long_dest-44, er0	rotr.l	@(44:16, er0)	; shift right arithmetic by one, disp16	test_carry_set		; H=0 N=1 Z=0 V=0 C=1	test_zero_clear	test_ovf_clear	test_neg_set	test_h_gr32  long_dest-44 er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 1010 0101 1010 0101	;; -> 1101 0010 1101 0010 1101 0010 1101 0010	cmp.l	#0xd2d2d2d2, @long_dest	beq	.Lldisp161	fail.Lldisp161:	mov	#0xa5a5a5a5, @long_destrotr_l_disp32_1:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	mov	#long_dest-666, er0	rotr.l	@(666:32, er0)	; shift right arithmetic by one, disp32	test_carry_set		; H=0 N=1 Z=0 V=0 C=1	test_zero_clear	test_ovf_clear	test_neg_set	test_h_gr32  long_dest-666 er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 1010 0101 1010 0101	;; -> 1101 0010 1101 0010 1101 0010 1101 0010	cmp.l	#0xd2d2d2d2, @long_dest	beq	.Lldisp321	fail.Lldisp321:	mov	#0xa5a5a5a5, @long_destrotr_l_abs16_1:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	rotr.l	@long_dest:16	; shift right arithmetic by one, abs16	test_carry_set		; H=0 N=1 Z=0 V=0 C=1	test_zero_clear	test_ovf_clear	test_neg_set	test_gr_a5a5 0		; Make sure ALL general regs not disturbed	test_gr_a5a5 1	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 1010 0101 1010 0101	;; -> 1101 0010 1101 0010 1101 0010 1101 0010	cmp.l	#0xd2d2d2d2, @long_dest	beq	.Llabs161	fail.Llabs161:	mov	#0xa5a5a5a5, @long_destrotr_l_abs32_1:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	rotr.l	@long_dest:32	; shift right arithmetic by one, abs32	test_carry_set		; H=0 N=1 Z=0 V=0 C=1	test_zero_clear	test_ovf_clear	test_neg_set	test_gr_a5a5 0		; Make sure ALL general regs not disturbed	test_gr_a5a5 1	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 1010 0101 1010 0101	;; -> 1101 0010 1101 0010 1101 0010 1101 0010	cmp.l	#0xd2d2d2d2, @long_dest	beq	.Llabs321	fail.Llabs321:	mov	#0xa5a5a5a5, @long_dest.endifrotr_l_reg32_2:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	rotr.l	#2, er0		; shift right arithmetic by two, register	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0	test_zero_clear	test_ovf_clear	test_neg_clear	; 1010 0101 1010 0101 1010 0101 1010 0101	; -> 0110 1001 0110 1001 0110 1001 0110 1001	test_h_gr32  0x69696969 er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7.if (sim_cpu == h8sx)rotr_l_ind_2:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	mov	#long_dest, er0	rotr.l	#2, @er0	; shift right arithmetic by two, indirect	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0	test_zero_clear	test_ovf_clear	test_neg_clear	test_h_gr32  long_dest er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 1010 0101 1010 0101	;; -> 0110 1001 0110 1001 0110 1001 0110 1001	cmp.l	#0x69696969, @long_dest	beq	.Llind2	fail.Llind2:	mov	#0xa5a5a5a5, @long_destrotr_l_postinc_2:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	mov	#long_dest, er0	rotr.l	#2, @er0+	; shift right arithmetic by two, postinc	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0	test_zero_clear	test_ovf_clear	test_neg_clear	test_h_gr32  long_dest+4 er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 1010 0101 1010 0101	;; -> 0110 1001 0110 1001 0110 1001 0110 1001	cmp.l	#0x69696969, @long_dest	beq	.Llpostinc2	fail.Llpostinc2:	mov	#0xa5a5a5a5, @long_destrotr_l_postdec_2:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	mov	#long_dest, er0	rotr.l	#2, @er0-	; shift right arithmetic by two, postdec	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0	test_zero_clear	test_ovf_clear	test_neg_clear	test_h_gr32  long_dest-4 er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 1010 0101 1010 0101	;; -> 0110 1001 0110 1001 0110 1001 0110 1001	cmp.l	#0x69696969, @long_dest	beq	.Llpostdec2	fail.Llpostdec2:	mov	#0xa5a5a5a5, @long_destrotr_l_preinc_2:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	mov	#long_dest-4, er0	rotr.l	#2, @+er0	; shift right arithmetic by two, preinc	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0	test_zero_clear	test_ovf_clear	test_neg_clear	test_h_gr32  long_dest er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 1010 0101 1010 0101	;; -> 0110 1001 0110 1001 0110 1001 0110 1001	cmp.l	#0x69696969, @long_dest	beq	.Llpreinc2	fail.Llpreinc2:	mov	#0xa5a5a5a5, @long_destrotr_l_predec_2:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	mov	#long_dest+4, er0	rotr.l	#2, @-er0	; shift right arithmetic by two, predec	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0	test_zero_clear	test_ovf_clear	test_neg_clear	test_h_gr32  long_dest er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 1010 0101 1010 0101	;; -> 0110 1001 0110 1001 0110 1001 0110 1001	cmp.l	#0x69696969, @long_dest	beq	.Llpredec2	fail.Llpredec2:	mov	#0xa5a5a5a5, @long_destrotr_l_disp2_2:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	mov	#long_dest-8, er0	rotr.l	#2, @(8:2, er0)	; shift right arithmetic by two, disp2	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0	test_zero_clear	test_ovf_clear	test_neg_clear	test_h_gr32  long_dest-8 er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 1010 0101 1010 0101	;; -> 0110 1001 0110 1001 0110 1001 0110 1001	cmp.l	#0x69696969, @long_dest	beq	.Lldisp22	fail.Lldisp22:	mov	#0xa5a5a5a5, @long_destrotr_l_disp16_2:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	mov	#long_dest-44, er0	rotr.l	#2, @(44:16, er0)	; shift right arithmetic by two, disp16	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0	test_zero_clear	test_ovf_clear	test_neg_clear	test_h_gr32  long_dest-44 er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 1010 0101 1010 0101	;; -> 0110 1001 0110 1001 0110 1001 0110 1001	cmp.l	#0x69696969, @long_dest	beq	.Lldisp162	fail.Lldisp162:	mov	#0xa5a5a5a5, @long_destrotr_l_disp32_2:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	mov	#long_dest-666, er0	rotr.l	#2, @(666:32, er0)	; shift right arithmetic by two, disp32	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0	test_zero_clear	test_ovf_clear	test_neg_clear	test_h_gr32  long_dest-666 er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 1010 0101 1010 0101	;; -> 0110 1001 0110 1001 0110 1001 0110 1001	cmp.l	#0x69696969, @long_dest	beq	.Lldisp322	fail.Lldisp322:	mov	#0xa5a5a5a5, @long_destrotr_l_abs16_2:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	rotr.l	#2, @long_dest:16	; shift right arithmetic by two, abs16	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0	test_zero_clear	test_ovf_clear	test_neg_clear	test_gr_a5a5 0		; Make sure ALL general regs not disturbed	test_gr_a5a5 1	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 1010 0101 1010 0101	;; -> 0110 1001 0110 1001 0110 1001 0110 1001	cmp.l	#0x69696969, @long_dest	beq	.Llabs162	fail.Llabs162:	mov	#0xa5a5a5a5, @long_destrotr_l_abs32_2:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	rotr.l	#2, @long_dest:32	; shift right arithmetic by two, abs32	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0	test_zero_clear	test_ovf_clear	test_neg_clear	test_gr_a5a5 0		; Make sure ALL general regs not disturbed	test_gr_a5a5 1	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 1010 0101 1010 0101	;; -> 0110 1001 0110 1001 0110 1001 0110 1001	cmp.l	#0x69696969, @long_dest	beq	.Llabs322	fail.Llabs322:	mov	#0xa5a5a5a5, @long_dest	.endif.endif	pass	exit 0
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