📄 rotr.s

📁 gdb-6.8 Linux下的调试程序最新版本
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	cmp.b	#0x69, @byte_dest	beq	.Lbabs322	fail.Lbabs322:	mov.b	#0xa5, @byte_dest.endif.if (sim_cpu)			; Not available in h8300 moderotr_w_reg16_1:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	rotr.w	r0		; shift right arithmetic by one	test_carry_set		; H=0 N=1 Z=0 V=0 C=1	test_zero_clear	test_ovf_clear	test_neg_set	test_h_gr16 0xd2d2 r0	; 1010 0101 1010 0101 -> 1101 0010 1101 0010	test_h_gr32 0xa5a5d2d2 er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7.if (sim_cpu == h8sx)rotr_w_ind_1:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	mov	#word_dest, er0	rotr.w	@er0	; shift right arithmetic by one, indirect	test_carry_set		; H=0 N=1 Z=0 V=0 C=1	test_zero_clear	test_ovf_clear	test_neg_set	test_h_gr32  word_dest er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 -> 1101 0010 1101 0010 	cmp.w	#0xd2d2, @word_dest	beq	.Lwind1	fail.Lwind1:	mov.w	#0xa5a5, @word_destrotr_w_postinc_1:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	mov	#word_dest, er0	rotr.w	@er0+	; shift right arithmetic by one, postinc	test_carry_set		; H=0 N=1 Z=0 V=0 C=1	test_zero_clear	test_ovf_clear	test_neg_set	test_h_gr32  word_dest+2 er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 -> 1101 0010 1101 0010 	cmp.w	#0xd2d2, @word_dest	beq	.Lwpostinc1	fail.Lwpostinc1:	mov.w	#0xa5a5, @word_destrotr_w_postdec_1:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	mov	#word_dest, er0	rotr.w	@er0-	; shift right arithmetic by one, postdec	test_carry_set		; H=0 N=1 Z=0 V=0 C=1	test_zero_clear	test_ovf_clear	test_neg_set	test_h_gr32  word_dest-2 er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 -> 1101 0010 1101 0010 	cmp.w	#0xd2d2, @word_dest	beq	.Lwpostdec1	fail.Lwpostdec1:	mov.w	#0xa5a5, @word_destrotr_w_preinc_1:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	mov	#word_dest-2, er0	rotr.w	@+er0	; shift right arithmetic by one, preinc	test_carry_set		; H=0 N=1 Z=0 V=0 C=1	test_zero_clear	test_ovf_clear	test_neg_set	test_h_gr32  word_dest er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 -> 1101 0010 1101 0010 	cmp.w	#0xd2d2, @word_dest	beq	.Lwpreinc1	fail.Lwpreinc1:	mov.w	#0xa5a5, @word_destrotr_w_predec_1:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	mov	#word_dest+2, er0	rotr.w	@-er0	; shift right arithmetic by one, predec	test_carry_set		; H=0 N=1 Z=0 V=0 C=1	test_zero_clear	test_ovf_clear	test_neg_set	test_h_gr32  word_dest er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 -> 1101 0010 1101 0010 	cmp.w	#0xd2d2, @word_dest	beq	.Lwpredec1	fail.Lwpredec1:	mov.w	#0xa5a5, @word_destrotr_w_disp2_1:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	mov	#word_dest-4, er0	rotr.w	@(4:2, er0)	; shift right arithmetic by one, disp2	test_carry_set		; H=0 N=1 Z=0 V=0 C=1	test_zero_clear	test_ovf_clear	test_neg_set	test_h_gr32  word_dest-4 er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 -> 1101 0010 1101 0010 	cmp.w	#0xd2d2, @word_dest	beq	.Lwdisp21	fail.Lwdisp21:	mov.w	#0xa5a5, @word_destrotr_w_disp16_1:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	mov	#word_dest-44, er0	rotr.w	@(44:16, er0)	; shift right arithmetic by one, disp16	test_carry_set		; H=0 N=1 Z=0 V=0 C=1	test_zero_clear	test_ovf_clear	test_neg_set	test_h_gr32  word_dest-44 er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 -> 1101 0010 1101 0010 	cmp.w	#0xd2d2, @word_dest	beq	.Lwdisp161	fail.Lwdisp161:	mov.w	#0xa5a5, @word_destrotr_w_disp32_1:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	mov	#word_dest-666, er0	rotr.w	@(666:32, er0)	; shift right arithmetic by one, disp32	test_carry_set		; H=0 N=1 Z=0 V=0 C=1	test_zero_clear	test_ovf_clear	test_neg_set	test_h_gr32  word_dest-666 er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 -> 1101 0010 1101 0010 	cmp.w	#0xd2d2, @word_dest	beq	.Lwdisp321	fail.Lwdisp321:	mov.w	#0xa5a5, @word_destrotr_w_abs16_1:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	rotr.w	@word_dest:16	; shift right arithmetic by one, abs16	test_carry_set		; H=0 N=1 Z=0 V=0 C=1	test_zero_clear	test_ovf_clear	test_neg_set	test_gr_a5a5 0		; Make sure ALL general regs not disturbed	test_gr_a5a5 1	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 -> 1101 0010 1101 0010 	cmp.w	#0xd2d2, @word_dest	beq	.Lwabs161	fail.Lwabs161:	mov.w	#0xa5a5, @word_destrotr_w_abs32_1:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	rotr.w	@word_dest:32	; shift right arithmetic by one, abs32	test_carry_set		; H=0 N=1 Z=0 V=0 C=1	test_zero_clear	test_ovf_clear	test_neg_set	test_gr_a5a5 0		; Make sure ALL general regs not disturbed	test_gr_a5a5 1	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 -> 1101 0010 1101 0010 	cmp.w	#0xd2d2, @word_dest	beq	.Lwabs321	fail.Lwabs321:	mov.w	#0xa5a5, @word_dest.endif	rotr_w_reg16_2:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	rotr.w	#2, r0		; shift right arithmetic by two	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0	test_zero_clear	test_ovf_clear	test_neg_clear	test_h_gr16 0x6969 r0	; 1010 0101 1010 0101 -> 0110 1001 0110 1001	test_h_gr32 0xa5a56969 er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7.if (sim_cpu == h8sx)rotr_w_ind_2:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	mov	#word_dest, er0	rotr.w	#2, @er0	; shift right arithmetic by two, indirect	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0	test_zero_clear	test_ovf_clear	test_neg_clear	test_h_gr32  word_dest er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 -> 0110 1001 0110 1001  	cmp.w	#0x6969, @word_dest	beq	.Lwind2	fail.Lwind2:	mov.w	#0xa5a5, @word_destrotr_w_postinc_2:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	mov	#word_dest, er0	rotr.w	#2, @er0+	; shift right arithmetic by two, postinc	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0	test_zero_clear	test_ovf_clear	test_neg_clear	test_h_gr32  word_dest+2 er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 -> 0110 1001 0110 1001  	cmp.w	#0x6969, @word_dest	beq	.Lwpostinc2	fail.Lwpostinc2:	mov.w	#0xa5a5, @word_destrotr_w_postdec_2:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	mov	#word_dest, er0	rotr.w	#2, @er0-	; shift right arithmetic by two, postdec	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0	test_zero_clear	test_ovf_clear	test_neg_clear	test_h_gr32  word_dest-2 er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 -> 0110 1001 0110 1001  	cmp.w	#0x6969, @word_dest	beq	.Lwpostdec2	fail.Lwpostdec2:	mov.w	#0xa5a5, @word_destrotr_w_preinc_2:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	mov	#word_dest-2, er0	rotr.w	#2, @+er0	; shift right arithmetic by two, preinc	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0	test_zero_clear	test_ovf_clear	test_neg_clear	test_h_gr32  word_dest er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 -> 0110 1001 0110 1001  	cmp.w	#0x6969, @word_dest	beq	.Lwpreinc2	fail.Lwpreinc2:	mov.w	#0xa5a5, @word_destrotr_w_predec_2:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	mov	#word_dest+2, er0	rotr.w	#2, @-er0	; shift right arithmetic by two, predec	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0	test_zero_clear	test_ovf_clear	test_neg_clear	test_h_gr32  word_dest er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 -> 0110 1001 0110 1001  	cmp.w	#0x6969, @word_dest	beq	.Lwpredec2	fail.Lwpredec2:	mov.w	#0xa5a5, @word_destrotr_w_disp2_2:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	mov	#word_dest-4, er0	rotr.w	#2, @(4:2, er0)	; shift right arithmetic by two, disp2	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0	test_zero_clear	test_ovf_clear	test_neg_clear	test_h_gr32  word_dest-4 er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 -> 0110 1001 0110 1001  	cmp.w	#0x6969, @word_dest	beq	.Lwdisp22	fail.Lwdisp22:	mov.w	#0xa5a5, @word_destrotr_w_disp16_2:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	mov	#word_dest-44, er0	rotr.w	#2, @(44:16, er0)	; shift right arithmetic by two, disp16	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0	test_zero_clear	test_ovf_clear	test_neg_clear	test_h_gr32  word_dest-44 er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 -> 0110 1001 0110 1001  	cmp.w	#0x6969, @word_dest	beq	.Lwdisp162	fail.Lwdisp162:	mov.w	#0xa5a5, @word_destrotr_w_disp32_2:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	mov	#word_dest-666, er0	rotr.w	#2, @(666:32, er0)	; shift right arithmetic by two, disp32	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0	test_zero_clear	test_ovf_clear	test_neg_clear	test_h_gr32  word_dest-666 er0	test_gr_a5a5 1		; Make sure other general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 -> 0110 1001 0110 1001  	cmp.w	#0x6969, @word_dest	beq	.Lwdisp322	fail.Lwdisp322:	mov.w	#0xa5a5, @word_destrotr_w_abs16_2:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	rotr.w	#2, @word_dest:16	; shift right arithmetic by two, abs16	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0	test_zero_clear	test_ovf_clear	test_neg_clear	test_gr_a5a5 0		; Make sure ALL general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 -> 0110 1001 0110 1001  	cmp.w	#0x6969, @word_dest	beq	.Lwabs162	fail.Lwabs162:	mov.w	#0xa5a5, @word_destrotr_w_abs32_2:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	rotr.w	#2, @word_dest:32	; shift right arithmetic by two, abs32	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0	test_zero_clear	test_ovf_clear	test_neg_clear	test_gr_a5a5 0		; Make sure ALL general regs not disturbed	test_gr_a5a5 2	test_gr_a5a5 2	test_gr_a5a5 3	test_gr_a5a5 4	test_gr_a5a5 5	test_gr_a5a5 6	test_gr_a5a5 7	; 1010 0101 1010 0101 -> 0110 1001 0110 1001  	cmp.w	#0x6969, @word_dest	beq	.Lwabs322	fail.Lwabs322:	mov.w	#0xa5a5, @word_dest.endifrotr_l_reg32_1:	set_grs_a5a5		; Fill all general regs with a fixed pattern	set_ccr_zero	rotr.l	er0		; shift right arithmetic by one, register	test_carry_set		; H=0 N=1 Z=0 V=0 C=1	test_zero_clear	test_ovf_clear	test_neg_set
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