📄 shar.s
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fail.Lbabs322: mov.b #0xa5, @byte_dest.endif.if (sim_cpu) ; Not available in h8300 modeshar_w_reg16_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero shar.w r0 ; shift right arithmetic by one;;; .word 0x1190 test_carry_set ; H=0 N=1 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_set test_h_gr16 0xd2d2 r0 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 test_h_gr32 0xa5a5d2d2 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7.if (sim_cpu == h8sx)shar_w_ind_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest, er0 shar.w @er0 ; shift right arithmetic by one, indirect;;; .word 0x7d80;;; .word 0x1190 test_carry_set ; H=0 N=1 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_set test_h_gr32 word_dest er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 cmp.w #0xd2d2, @word_dest beq .Lwind1 fail.Lwind1: mov.w #0xa5a5, @word_destshar_w_postinc_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest, er0 shar.w @er0+ ; shift right arithmetic by one, postinc;;; .word 0x0154;;; .word 0x6d08;;; .word 0x1190 test_carry_set ; H=0 N=1 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_set test_h_gr32 word_dest+2 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 cmp.w #0xd2d2, @word_dest beq .Lwpostinc1 fail.Lwpostinc1: mov.w #0xa5a5, @word_destshar_w_postdec_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest, er0 shar.w @er0- ; shift right arithmetic by one, postdec;;; .word 0x0156;;; .word 0x6d08;;; .word 0x1190 test_carry_set ; H=0 N=1 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_set test_h_gr32 word_dest-2 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 cmp.w #0xd2d2, @word_dest beq .Lwpostdec1 fail.Lwpostdec1: mov.w #0xa5a5, @word_destshar_w_preinc_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest-2, er0 shar.w @+er0 ; shift right arithmetic by one, preinc;;; .word 0x0155;;; .word 0x6d08;;; .word 0x1190 test_carry_set ; H=0 N=1 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_set test_h_gr32 word_dest er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 cmp.w #0xd2d2, @word_dest beq .Lwpreinc1 fail.Lwpreinc1: mov.w #0xa5a5, @word_destshar_w_predec_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest+2, er0 shar.w @-er0 ; shift right arithmetic by one, predec;;; .word 0x0157;;; .word 0x6d08;;; .word 0x1190 test_carry_set ; H=0 N=1 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_set test_h_gr32 word_dest er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 cmp.w #0xd2d2, @word_dest beq .Lwpredec1 fail.Lwpredec1: mov.w #0xa5a5, @word_destshar_w_disp2_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest-4, er0 shar.w @(4:2, er0) ; shift right arithmetic by one, disp2;;; .word 0x0156;;; .word 0x6908;;; .word 0x1190 test_carry_set ; H=0 N=1 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_set test_h_gr32 word_dest-4 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 cmp.w #0xd2d2, @word_dest beq .Lwdisp21 fail.Lwdisp21: mov.w #0xa5a5, @word_destshar_w_disp16_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest-44, er0 shar.w @(44:16, er0) ; shift right arithmetic by one, disp16;;; .word 0x0154;;; .word 0x6f08;;; .word 44;;; .word 0x1190 test_carry_set ; H=0 N=1 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_set test_h_gr32 word_dest-44 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 cmp.w #0xd2d2, @word_dest beq .Lwdisp161 fail.Lwdisp161: mov.w #0xa5a5, @word_destshar_w_disp32_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest-666, er0 shar.w @(666:32, er0) ; shift right arithmetic by one, disp32;;; .word 0x7884;;; .word 0x6b28;;; .long 666;;; .word 0x1190 test_carry_set ; H=0 N=1 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_set test_h_gr32 word_dest-666 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 cmp.w #0xd2d2, @word_dest beq .Lwdisp321 fail.Lwdisp321: mov.w #0xa5a5, @word_destshar_w_abs16_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero shar.w @word_dest:16 ; shift right arithmetic by one, abs16;;; .word 0x6b18;;; .word word_dest;;; .word 0x1190 test_carry_set ; H=0 N=1 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_set test_gr_a5a5 0 ; Make sure ALL general regs not disturbed test_gr_a5a5 1 test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 cmp.w #0xd2d2, @word_dest beq .Lwabs161 fail.Lwabs161: mov.w #0xa5a5, @word_destshar_w_abs32_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero shar.w @word_dest:32 ; shift right arithmetic by one, abs32;;; .word 0x6b38;;; .long word_dest;;; .word 0x1190 test_carry_set ; H=0 N=1 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_set test_gr_a5a5 0 ; Make sure ALL general regs not disturbed test_gr_a5a5 1 test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 cmp.w #0xd2d2, @word_dest beq .Lwabs321 fail.Lwabs321: mov.w #0xa5a5, @word_dest.endif shar_w_reg16_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero shar.w #2, r0 ; shift right arithmetic by two;;; .word 0x11d0 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_set test_h_gr16 0xe969 r0 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 test_h_gr32 0xa5a5e969 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7.if (sim_cpu == h8sx)shar_w_ind_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest, er0 shar.w #2, @er0 ; shift right arithmetic by two, indirect;;; .word 0x7d80;;; .word 0x11d0 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_set test_h_gr32 word_dest er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 cmp.w #0xe969, @word_dest beq .Lwind2 fail.Lwind2: mov.w #0xa5a5, @word_destshar_w_postinc_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest, er0 shar.w #2, @er0+ ; shift right arithmetic by two, postinc;;; .word 0x0154;;; .word 0x6d08;;; .word 0x11d0 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_set test_h_gr32 word_dest+2 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 cmp.w #0xe969, @word_dest beq .Lwpostinc2 fail.Lwpostinc2: mov.w #0xa5a5, @word_destshar_w_postdec_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest, er0 shar.w #2, @er0- ; shift right arithmetic by two, postdec;;; .word 0x0156;;; .word 0x6d08;;; .word 0x11d0 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_set test_h_gr32 word_dest-2 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 cmp.w #0xe969, @word_dest beq .Lwpostdec2 fail.Lwpostdec2: mov.w #0xa5a5, @word_destshar_w_preinc_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest-2, er0 shar.w #2, @+er0 ; shift right arithmetic by two, preinc;;; .word 0x0155;;; .word 0x6d08;;; .word 0x11d0 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_set test_h_gr32 word_dest er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 cmp.w #0xe969, @word_dest beq .Lwpreinc2 fail.Lwpreinc2: mov.w #0xa5a5, @word_destshar_w_predec_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest+2, er0 shar.w #2, @-er0 ; shift right arithmetic by two, predec;;; .word 0x0157;;; .word 0x6d08;;; .word 0x11d0 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_set test_h_gr32 word_dest er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 cmp.w #0xe969, @word_dest beq .Lwpredec2 fail.Lwpredec2: mov.w #0xa5a5, @word_destshar_w_disp2_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest-4, er0 shar.w #2, @(4:2, er0) ; shift right arithmetic by two, disp2;;; .word 0x0156;;; .word 0x6908;;; .word 0x11d0 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_set test_h_gr32 word_dest-4 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 cmp.w #0xe969, @word_dest beq .Lwdisp22 fail.Lwdisp22: mov.w #0xa5a5, @word_destshar_w_disp16_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest-44, er0 shar.w #2, @(44:16, er0) ; shift right arithmetic by two, disp16;;; .word 0x0154;;; .word 0x6f08;;; .word 44;;; .word 0x11d0 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_set test_h_gr32 word_dest-44 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 cmp.w #0xe969, @word_dest beq .Lwdisp162 fail.Lwdisp162: mov.w #0xa5a5, @word_destshar_w_disp32_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #word_dest-666, er0 shar.w #2, @(666:32, er0) ; shift right arithmetic by two, disp32;;; .word 0x7884;;; .word 0x6b28;;; .long 666;;; .word 0x11d0 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_set test_h_gr32 word_dest-666 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 cmp.w #0xe969, @word_dest beq .Lwdisp322 fail.Lwdisp322: mov.w #0xa5a5, @word_destshar_w_abs16_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero shar.w #2, @word_dest:16 ; shift right arithmetic by two, abs16;;; .word 0x6b18;;; .word word_dest;;; .word 0x11d0 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_set test_gr_a5a5 0 ; Make sure ALL general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 cmp.w #0xe969, @word_dest beq .Lwabs162 fail.Lwabs162: mov.w #0xa5a5, @word_destshar_w_abs32_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero shar.w #2, @word_dest:32 ; shift right arithmetic by two, abs32;;; .word 0x6b38;;; .long word_dest;;; .word 0x11d0 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_set test_gr_a5a5 0 ; Make sure ALL general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 cmp.w #0xe969, @word_dest beq .Lwabs322 fail.Lwabs322: mov.w #0xa5a5, @word_dest.endifshar_l_reg32_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero shar.l er0 ; shift right arithmetic by one, register;;; .word 0x11b0 test_carry_set ; H=0 N=1 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_set ; 1010 0101 1010 0101 1010 0101 1010 0101 ; -> 1101 0010 1101 0010 1101 0010 1101 0010 test_h_gr32 0xd2d2d2d2 er0⌨️ 快捷键说明
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