📄 rotl.s
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# Hitachi H8 testcase 'rotl'# mach(): all# as(h8300): --defsym sim_cpu=0# as(h8300h): --defsym sim_cpu=1# as(h8300s): --defsym sim_cpu=2# as(h8sx): --defsym sim_cpu=3# ld(h8300h): -m h8300helf# ld(h8300s): -m h8300self# ld(h8sx): -m h8300sxelf .include "testutils.inc" start .databyte_dest: .byte 0xa5 .align 2word_dest: .word 0xa5a5 .align 4long_dest: .long 0xa5a5a5a5 .textrotl_b_reg8_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero rotl.b r0l ; shift left arithmetic by one test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr16 0xa54b r0 ; 1010 0101 -> 0100 1011.if (sim_cpu) test_h_gr32 0xa5a5a54b er0.endif test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7.if (sim_cpu == h8sx)rotl_b_ind_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #byte_dest, er0 rotl.b @er0 ; shift right arithmetic by one, indirect test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 byte_dest er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0100 1011 cmp.b #0x4b, @byte_dest beq .Lbind1 fail.Lbind1: mov.b #0xa5, @byte_destrotl_b_indexb16_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov.b #5, r0l rotl.b @(byte_dest-5:16, r0.b) ; indexed byte/byte test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 0xa5a5a505 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0100 1011 cmp.b #0x4b, @byte_dest beq .Lbindexb161 fail.Lbindexb161: mov.b #0xa5, @byte_destrotl_b_indexw16_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov.w #256, r0 rotl.b @(byte_dest-256:16, r0.w) ; indexed byte/word test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 0xa5a50100 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0100 1011 cmp.b #0x4b, @byte_dest beq .Lbindexw161 fail.Lbindexw161: mov.b #0xa5, @byte_destrotl_b_indexl16_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov.l #0xffffffff, er0 rotl.b @(byte_dest+1:16, er0.l) ; indexed byte/long test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 0xffffffff er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0100 1011 cmp.b #0x4b, @byte_dest beq .Lbindexl161 fail.Lbindexl161: mov.b #0xa5, @byte_destrotl_b_indexb32_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov.b #5, r1l rotl.b @(byte_dest-5:32, r1.b) ; indexed byte/byte test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 0xa5a5a505 er1 test_gr_a5a5 0 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0100 1011 cmp.b #0x4b, @byte_dest beq .Lbindexb321 fail.Lbindexb321: mov.b #0xa5, @byte_destrotl_b_indexw32_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov.w #256, r1 rotl.b @(byte_dest-256:32, r1.w) ; indexed byte/word test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 0xa5a50100 er1 test_gr_a5a5 0 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0100 1011 cmp.b #0x4b, @byte_dest beq .Lbindexw321 fail.Lbindexw321: mov.b #0xa5, @byte_destrotl_b_indexl32_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov.l #0xffffffff, er1 rotl.b @(byte_dest+1:32, er1.l) ; indexed byte/long test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 0xffffffff er1 test_gr_a5a5 0 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 0100 1011 cmp.b #0x4b, @byte_dest beq .Lbindexl321 fail.Lbindexl321: mov.b #0xa5, @byte_dest.endifrotl_b_reg8_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero rotl.b #2, r0l ; shift left arithmetic by two test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_set test_h_gr16 0xa596 r0 ; 1010 0101 -> 1001 0110.if (sim_cpu) test_h_gr32 0xa5a5a596 er0.endif test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7.if (sim_cpu == h8sx)rotl_b_ind_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov #byte_dest, er0 rotl.b #2, @er0 ; shift right arithmetic by one, indirect test_carry_clear ; H=0 N=1 Z=0 C=0 test_zero_clear test_ovf_clear test_neg_set test_h_gr32 byte_dest er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 1001 0110 cmp.b #0x96, @byte_dest beq .Lbind2 fail.Lbind2: mov.b #0xa5, @byte_destrotl_b_indexb16_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov.b #5, r0l rotl.b #2, @(byte_dest-5:16, r0.b) ; indexed byte/byte test_carry_clear ; H=0 N=1 Z=0 C=0 test_zero_clear test_ovf_clear test_neg_set test_h_gr32 0xa5a5a505 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 1001 0110 cmp.b #0x96, @byte_dest beq .Lbindexb162 fail.Lbindexb162: mov.b #0xa5, @byte_destrotl_b_indexw16_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov.w #256, r0 rotl.b #2, @(byte_dest-256:16, r0.w) ; indexed byte/word test_carry_clear ; H=0 N=1 Z=0 C=0 test_zero_clear test_ovf_clear test_neg_set test_h_gr32 0xa5a50100 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 1001 0110 cmp.b #0x96, @byte_dest beq .Lbindexw162 fail.Lbindexw162: mov.b #0xa5, @byte_destrotl_b_indexl16_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov.l #0xffffffff, er0 rotl.b #2, @(byte_dest+1:16, er0.l) ; indexed byte/long test_carry_clear ; H=0 N=1 Z=0 C=0 test_zero_clear test_ovf_clear test_neg_set test_h_gr32 0xffffffff er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 1001 0110 cmp.b #0x96, @byte_dest beq .Lbindexl162 fail.Lbindexl162: mov.b #0xa5, @byte_destrotl_b_indexb32_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov.b #5, r1l rotl.b #2, @(byte_dest-5:32, r1.b) ; indexed byte/byte test_carry_clear ; H=0 N=1 Z=0 C=0 test_zero_clear test_ovf_clear test_neg_set test_h_gr32 0xa5a5a505 er1 test_gr_a5a5 0 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 1001 0110 cmp.b #0x96, @byte_dest beq .Lbindexb322 fail.Lbindexb322: mov.b #0xa5, @byte_destrotl_b_indexw32_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov.w #256, r1 rotl.b #2, @(byte_dest-256:32, r1.w) ; indexed byte/word test_carry_clear ; H=0 N=1 Z=0 C=0 test_zero_clear test_ovf_clear test_neg_set test_h_gr32 0xa5a50100 er1 test_gr_a5a5 0 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 1001 0110 cmp.b #0x96, @byte_dest beq .Lbindexw322 fail.Lbindexw322: mov.b #0xa5, @byte_destrotl_b_indexl32_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov.l #0xffffffff, er1 rotl.b #2, @(byte_dest+1:32, er1.l) ; indexed byte/long test_carry_clear ; H=0 N=1 Z=0 C=0 test_zero_clear test_ovf_clear test_neg_set test_h_gr32 0xffffffff er1 test_gr_a5a5 0 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 -> 1001 0110 cmp.b #0x96, @byte_dest beq .Lbindexl322 fail.Lbindexl322: mov.b #0xa5, @byte_dest.endif.if (sim_cpu) ; Not available in h8300 moderotl_w_reg16_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero rotl.w r0 ; shift left arithmetic by one test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr16 0x4b4b r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 test_h_gr32 0xa5a54b4b er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7.if (sim_cpu == h8sx)rotl_w_indexb16_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov.b #5, r0l rotl.w @(word_dest-10:16, r0.b) ; indexed word/byte test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 0xa5a5a505 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 cmp.w #0x4b4b, @word_dest beq .Lwindexb161 fail.Lwindexb161: mov.w #0xa5a5, @word_destrotl_w_indexw16_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov.w #256, r0 rotl.w @(word_dest-512:16, r0.w) ; indexed word/word test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 0xa5a50100 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 cmp.w #0x4b4b, @word_dest beq .Lwindexw161 fail.Lwindexw161: mov.w #0xa5a5, @word_destrotl_w_indexl16_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov.l #0xffffffff, er0 rotl.w @(word_dest+2:16, er0.l) ; indexed word/long test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 0xffffffff er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 cmp.w #0x4b4b, @word_dest beq .Lwindexl161 fail.Lwindexl161: mov.w #0xa5a5, @word_destrotl_w_indexb32_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov.b #5, r1l rotl.w @(word_dest-10:32, r1.b) ; indexed word/byte test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 0xa5a5a505 er1 test_gr_a5a5 0 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 cmp.w #0x4b4b, @word_dest beq .Lwindexb321 fail.Lwindexb321: mov.w #0xa5a5, @word_destrotl_w_indexw32_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero mov.w #256, r1 rotl.w @(word_dest-512:32, r1.w) ; indexed word/byte test_carry_set ; H=0 N=0 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_clear test_h_gr32 0xa5a50100 er1 test_gr_a5a5 0 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 cmp.w #0x4b4b, @word_dest beq .Lwindexw321 fail⌨️ 快捷键说明
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