addl.s

gdb-6.8 Linux下的调试程序 最新版本

# Hitachi H8 testcase 'add.l'
# mach(): h8300h h8300s h8sx
# as(h8300h):	--defsym sim_cpu=1
# as(h8300s):	--defsym sim_cpu=2
# as(h8sx):	--defsym sim_cpu=3
# ld(h8300h):	-m h8300helf
# ld(h8300s):	-m h8300self
# ld(h8sx):	-m h8300sxelf	

	.include "testutils.inc"

	# Instructions tested:
	# add.l xx:3, erd
	# add.l xx:16, erd
	# add.l xx:32, erd
	# add.l xx:16, @erd
	# add.l xx:16, @erd+
	# add.l xx:16, @erd-
	# add.l xx:16, @+erd
	# add.l xx:16, @-erd
	# add.l xx:16, @(dd:2, erd)
	# add.l xx:16, @(dd:16, erd)
	# add.l xx:16, @(dd:32, erd)
	# add.l xx:16, @aa:16
	# add.l xx:16, @aa:32
	# add.l xx:32, @erd+
	# add.l xx:32, @erd-
	# add.l xx:32, @+erd
	# add.l xx:32, @-erd
	# add.l xx:32, @(dd:2, erd)
	# add.l xx:32, @(dd:16, erd)
	# add.l xx:32, @(dd:32, erd)
	# add.l xx:32, @aa:16
	# add.l xx:32, @aa:32
	# add.l ers, erd
	# add.l ers, @erd
	# add.l ers, @erd+
	# add.l ers, @erd-
	# add.l ers, @+erd
	# add.l ers, @-erd
	# add.l ers, @(dd:2, erd)
	# add.l ers, @(dd:16, erd)
	# add.l ers, @(dd:32, erd)
	# add.l ers, @aa:16
	# add.l ers, @aa:32
	# add.l ers, erd
	# add.l @ers, erd
	# add.l @ers+, erd
	# add.l @ers-, erd
	# add.l @+ers, erd
	# add.l @-ers, erd
	# add.l @(dd:2, ers), erd
	# add.l @(dd:16, ers), erd
	# add.l @(dd:32, ers), erd
	# add.l @aa:16, erd
	# add.l @aa:32, erd
	# add.l @ers, @erd
	# add.l @ers+, @erd+
	# add.l @ers-, @erd-
	# add.l @+ers, +@erd
	# add.l @-ers, @-erd
	# add.l @(dd:2, ers), @(dd:2, erd)
	# add.l @(dd:16, ers), @(dd:16, erd)
	# add.l @(dd:32, ers), @(dd:32, erd)
	# add.l @aa:16, @aa:16
	# add.l @aa:32, @aa:32

	start

	.data
	.align	4
long_src:
	.long	0x12345678
long_dst:
	.long	0x87654321

	.text

	;;
	;; Add long from immediate source
	;; 

.if (sim_cpu == h8sx)
add_l_imm3_to_reg32:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; add.l #xx:3, erd
	add.l	#0x3:3, er0	; Immediate 16-bit operand
;;;	.word	0x0ab8

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32 0xa5a5a5a8 er0

	test_gr_a5a5 1		; Make sure other general regs not disturbed
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

add_l_imm16_to_reg32:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; add.l #xx:16, erd
	add.l	#0x1234, er0	; Immediate 16-bit operand
;;;	.word	0x7a18
;;;	.word	0x1234

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32 0xa5a5b7d9 er0

	test_gr_a5a5 1		; Make sure other general regs not disturbed
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7
.endif

add_l_imm32_to_reg32:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; add.l #xx:32, erd
	add.l	#0x12345678, er0	; Immediate 32-bit operand
;;;	.word	0x7a10
;;;	.long	0x12345678

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32 0xb7d9fc1d er0

	test_gr_a5a5 1		; Make sure other general regs not disturbed
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

.if (sim_cpu == h8sx)
add_l_imm16_to_indirect:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; add.l #xx:16, @erd
	mov.l	#long_dst, er1
	add.l	#0xdead:16, @er1	; Register indirect operand
;;;	.word	0x010e
;;;	.word	0x0110
;;;	.word	0xdead

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	long_dst, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	#0x876621ce, @long_dst
	beq	.Lnext11
	fail
.Lnext11:
	mov.l	#0x87654321, @long_dst	; Initialize it again for the next use.

add_l_imm16_to_postinc:		; post-increment from imm16 to mem
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; add.l #xx:16, @erd+
	mov.l	#long_dst, er1
	add.l	#0xdead:16, @er1+	; Imm16, register post-incr operands.
;;;	.word	0x010e
;;;	.word	0x8110
;;;	.word	0xdead

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	long_dst+4, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	#0x876621ce, @long_dst
	beq	.Lnext12
	fail
.Lnext12:
	mov.l	#0x87654321, @long_dst	; initialize it again for the next use.

add_l_imm16_to_postdec:		; post-decrement from imm16 to mem
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; add.l #xx:16, @erd-
	mov.l	#long_dst, er1
	add.l	#0xdead:16, @er1-	; Imm16, register post-decr operands.
;;;	.word	0x010e
;;;	.word	0xa110
;;;	.word	0xdead

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	long_dst-4, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	#0x876621ce, @long_dst
	beq	.Lnext13
	fail
.Lnext13:
	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.

add_l_imm16_to_preinc:		; pre-increment from register to mem
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; add.l #xx:16, @+erd
	mov.l	#long_dst-4, er1
	add.l	#0xdead:16, @+er1	; Imm16, register pre-incr operands
;;;	.word	0x010e
;;;	.word	0x9110
;;;	.word	0xdead

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	long_dst, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	#0x876621ce, @long_dst
	beq	.Lnext14
	fail
.Lnext14:
	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.

add_l_imm16_to_predec:		; pre-decrement from register to mem
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; add.l #xx:16, @-erd
	mov.l	#long_dst+4, er1
	add.l	#0xdead:16, @-er1	; Imm16, register pre-decr operands
;;;	.word	0x010e
;;;	.word	0xb110
;;;	.word	0xdead

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	long_dst, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	#0x876621ce, @long_dst
	beq	.Lnext15
	fail
.Lnext15:
	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.

add_l_imm16_to_disp2:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; add.l #xx:16, @(dd:2, erd)
	mov.l	#long_dst-12, er1
	add.l	#0xdead:16, @(12:2, er1) ; Imm16, reg plus 2-bit disp. operand
;;;	.word	0x010e
;;;	.word	0x3110
;;;	.word	0xdead

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	long_dst-12, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	#0x876621ce, @long_dst
	beq	.Lnext16
	fail
.Lnext16:
	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.

add_l_imm16_to_disp16:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; add.l #xx:16, @(dd:16, erd)
	mov.l	#long_dst-4, er1
	add.l	#0xdead:16, @(4:16, er1)	; Register plus 16-bit disp. operand
;;;	.word	0x010e
;;;	.word	0xc110
;;;	.word	0xdead
;;;	.word	0x0004

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	long_dst-4, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	#0x876621ce, @long_dst
	beq	.Lnext17
	fail
.Lnext17:
	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.

add_l_imm16_to_disp32:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; add.l #xx:16, @(dd:32, erd)
	mov.l	#long_dst-8, er1
	add.l	#0xdead:16, @(8:32, er1)   ; Register plus 32-bit disp. operand
;;;	.word	0x010e
;;;	.word	0xc910
;;;	.word	0xdead
;;;	.long	8

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	long_dst-8, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	#0x876621ce, @long_dst
	beq	.Lnext18
	fail
.Lnext18:
	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.

add_l_imm16_to_abs16:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; add.l #xx:16, @aa:16
	add.l	#0xdead:16, @long_dst:16	; 16-bit address-direct operand
;;;	.word	0x010e
;;;	.word	0x4010
;;;	.word	0xdead
;;;	.word	@long_dst

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
	test_gr_a5a5 1		; (first, because on h8/300 we must use one
	test_gr_a5a5 2		; to examine the destination memory).
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	#0x876621ce, @long_dst
	beq	.Lnext19
	fail
.Lnext19:
	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.

add_l_imm16_to_abs32:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; add.l #xx:16, @aa:32
	add.l	#0xdead:16, @long_dst:32	; 32-bit address-direct operand
;;;	.word	0x010e
;;;	.word	0x4810
;;;	.word	0xdead
;;;	.long	@long_dst

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
	test_gr_a5a5 1		; (first, because on h8/300 we must use one
	test_gr_a5a5 2		; to examine the destination memory).
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	#0x876621ce, @long_dst
	beq	.Lnext20
	fail
.Lnext20:
	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.

add_l_imm32_to_indirect:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; add.l #xx:32, @erd
	mov.l	#long_dst, er1
	add.l	#0xcafedead:32, @er1	; Register indirect operand
;;;	.word	0x010e
;;;	.word	0x0118
;;;	.long	0xcafedead

	;; test ccr		; H=0 N=0 Z=0 V=1 C=1
	test_neg_clear
	test_zero_clear
	test_ovf_set
	test_carry_set

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	long_dst, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	#0x526421ce, @long_dst
	beq	.Lnext21
	fail
.Lnext21:
	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.

add_l_imm32_to_postinc:		; post-increment from imm32 to mem
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; add.l #xx:32, @erd+
	mov.l	#long_dst, er1
	add.l	#0xcafedead:32, @er1+	; Imm32, register post-incr operands.
;;;	.word	0x010e
;;;	.word	0x8118
;;;	.long	0xcafedead

	;; test ccr		; H=0 N=0 Z=0 V=1 C=1
	test_neg_clear
	test_zero_clear
	test_ovf_set
	test_carry_set

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	long_dst+4, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	#0x526421ce, @long_dst
	beq	.Lnext22
	fail
.Lnext22:
	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.

add_l_imm32_to_postdec:		; post-decrement from imm32 to mem
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; add.l #xx:32, @erd-
	mov.l	#long_dst, er1
	add.l	#0xcafedead:32, @er1-	; Imm32, register post-decr operands.
;;;	.word	0x010e
;;;	.word	0xa118
;;;	.long	0xcafedead

	;; test ccr		; H=0 N=0 Z=0 V=1 C=1
	test_neg_clear
	test_zero_clear
	test_ovf_set
	test_carry_set

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	long_dst-4, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	#0x526421ce, @long_dst
	beq	.Lnext23
	fail
.Lnext23:
	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.

add_l_imm32_to_preinc:		; pre-increment from register to mem
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; add.l #xx:32, @+erd
	mov.l	#long_dst-4, er1
	add.l	#0xcafedead:32, @+er1	; Imm32, register pre-incr operands
;;;	.word	0x010e
;;;	.word	0x9118
;;;	.long	0xcafedead

	;; test ccr		; H=0 N=0 Z=0 V=1 C=1
	test_neg_clear
	test_zero_clear
	test_ovf_set
	test_carry_set

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	long_dst, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.l	#0x526421ce, @long_dst
	beq	.Lnext24
	fail
.Lnext24:
	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.