📄 smu.cgs
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# frv testcase for smu $GRi,$GRj# mach: fr405 fr450 .include "../testutils.inc" start .global smusmu1: ; Positive operands set_gr_immed 3,gr7 ; multiply small numbers set_gr_immed 2,gr8 smu gr7,gr8 test_gr_immed 3,gr7 test_gr_immed 2,gr8 test_spr_immed 6,iacc0l test_spr_immed 0,iacc0hsmu2: set_gr_immed 1,gr7 ; multiply by 1 set_gr_immed 2,gr8 smu gr7,gr8 test_gr_immed 1,gr7 test_gr_immed 2,gr8 test_spr_immed 2,iacc0l test_spr_immed 0,iacc0hsmu3: set_gr_immed 2,gr7 ; multiply by 1 set_gr_immed 1,gr8 smu gr7,gr8 test_gr_immed 1,gr8 test_gr_immed 2,gr7 test_spr_immed 2,iacc0l test_spr_immed 0,iacc0hsmu4: set_gr_immed 0,gr7 ; multiply by 0 set_gr_immed 2,gr8 smu gr7,gr8 test_gr_immed 2,gr8 test_gr_immed 0,gr7 test_spr_immed 0,iacc0l test_spr_immed 0,iacc0hsmu5: set_gr_immed 2,gr7 ; multiply by 0 set_gr_immed 0,gr8 smu gr7,gr8 test_gr_immed 0,gr8 test_gr_immed 2,gr7 test_spr_immed 0,iacc0l test_spr_immed 0,iacc0hsmu6: set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result set_gr_immed 2,gr8 smu gr7,gr8 test_gr_immed 2,gr8 test_gr_limmed 0x3fff,0xffff,gr7 test_spr_limmed 0x7fff,0xfffe,iacc0l test_spr_immed 0,iacc0hsmu7: set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result set_gr_immed 2,gr8 smu gr7,gr8 test_gr_immed 2,gr8 test_gr_limmed 0x4000,0x0000,gr7 test_spr_limmed 0x8000,0x0000,iacc0l test_spr_immed 0,iacc0hsmu8: set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result set_gr_immed 4,gr8 smu gr7,gr8 test_gr_immed 4,gr8 test_gr_limmed 0x4000,0x0000,gr7 test_spr_immed 0,iacc0l test_spr_immed 1,iacc0hsmu9: set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result set_gr_limmed 0x7fff,0xffff,gr8 smu gr7,gr8 test_gr_limmed 0x7fff,0xffff,gr8 test_gr_limmed 0x7fff,0xffff,gr7 test_spr_immed 0x00000001,iacc0l test_spr_limmed 0x3fff,0xffff,iacc0hsmu10: ; Mixed operands set_gr_immed -3,gr7 ; multiply small numbers set_gr_immed 2,gr8 smu gr7,gr8 test_gr_immed 2,gr8 test_gr_immed -3,gr7 test_spr_immed -6,iacc0l test_spr_immed -1,iacc0hsmu11: set_gr_immed 3,gr7 ; multiply small numbers set_gr_immed -2,gr8 smu gr7,gr8 test_gr_immed -2,gr8 test_gr_immed 3,gr7 test_spr_immed -6,iacc0l test_spr_immed -1,iacc0hsmu12: set_gr_immed 1,gr7 ; multiply by 1 set_gr_immed -2,gr8 smu gr7,gr8 test_gr_immed -2,gr8 test_gr_immed 1,gr7 test_spr_immed -2,iacc0l test_spr_immed -1,iacc0hsmu13: set_gr_immed -2,gr7 ; multiply by 1 set_gr_immed 1,gr8 smu gr7,gr8 test_gr_immed 1,gr8 test_gr_immed -2,gr7 test_spr_immed -2,iacc0l test_spr_immed -1,iacc0hsmu14: set_gr_immed 0,gr7 ; multiply by 0 set_gr_immed -2,gr8 smu gr7,gr8 test_gr_immed -2,gr8 test_gr_immed 0,gr7 test_spr_immed 0,iacc0l test_spr_immed 0,iacc0hsmu15: set_gr_immed -2,gr7 ; multiply by 0 set_gr_immed 0,gr8 smu gr7,gr8 test_gr_immed 0,gr8 test_gr_immed -2,gr7 test_spr_immed 0,iacc0l test_spr_immed 0,iacc0hsmu16: set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result set_gr_immed -2,gr8 smu gr7,gr8 test_gr_immed -2,gr8 test_gr_limmed 0x2000,0x0001,gr7 test_spr_limmed 0xbfff,0xfffe,iacc0l test_spr_limmed 0xffff,0xffff,iacc0hsmu17: set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result set_gr_immed -2,gr8 smu gr7,gr8 test_gr_immed -2,gr8 test_gr_limmed 0x4000,0x0000,gr7 test_spr_limmed 0x8000,0x0000,iacc0l test_spr_limmed 0xffff,0xffff,iacc0hsmu18: set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result set_gr_immed -2,gr8 smu gr7,gr8 test_gr_immed -2,gr8 test_gr_limmed 0x4000,0x0001,gr7 test_spr_limmed 0x7fff,0xfffe,iacc0l test_spr_limmed 0xffff,0xffff,iacc0hsmu19: set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result set_gr_immed -4,gr8 smu gr7,gr8 test_gr_immed -4,gr8 test_gr_limmed 0x4000,0x0000,gr7 test_spr_limmed 0x0000,0x0000,iacc0l test_spr_limmed 0xffff,0xffff,iacc0hsmu20: set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result set_gr_limmed 0x8000,0x0000,gr8 smu gr7,gr8 test_gr_limmed 0x8000,0x0000,gr8 test_gr_limmed 0x7fff,0xffff,gr7 test_spr_limmed 0x8000,0x0000,iacc0l test_spr_limmed 0xc000,0x0000,iacc0hsmu21: ; Negative operands set_gr_immed -3,gr7 ; multiply small numbers set_gr_immed -2,gr8 smu gr7,gr8 test_gr_immed -2,gr8 test_gr_immed -3,gr7 test_spr_immed 6,iacc0l test_spr_immed 0,iacc0hsmu22: set_gr_immed -1,gr7 ; multiply by 1 set_gr_immed -2,gr8 smu gr7,gr8 test_gr_immed -2,gr8 test_gr_immed -1,gr7 test_spr_immed 2,iacc0l test_spr_immed 0,iacc0hsmu23: set_gr_immed -2,gr7 ; multiply by 1 set_gr_immed -1,gr8 smu gr7,gr8 test_gr_immed -1,gr8 test_gr_immed -2,gr7 test_spr_immed 2,iacc0l test_spr_immed 0,iacc0hsmu24: set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result set_gr_immed -2,gr8 smu gr7,gr8 test_gr_immed -2,gr8 test_gr_limmed 0xc000,0x0001,gr7 test_spr_limmed 0x7fff,0xfffe,iacc0l test_spr_immed 0,iacc0hsmu25: set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result set_gr_immed -2,gr8 smu gr7,gr8 test_gr_immed -2,gr8 test_gr_limmed 0xc000,0x0000,gr7 test_spr_limmed 0x8000,0x0000,iacc0l test_spr_immed 0,iacc0hsmu26: set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result set_gr_immed -4,gr8 smu gr7,gr8 test_gr_immed -4,gr8 test_gr_limmed 0xc000,0x0000,gr7 test_spr_immed 0x00000000,iacc0l test_spr_immed 1,iacc0hsmu27: set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result set_gr_limmed 0x8000,0x0001,gr8 smu gr7,gr8 test_gr_limmed 0x8000,0x0001,gr8 test_gr_limmed 0x8000,0x0001,gr7 test_spr_immed 0x00000001,iacc0l test_spr_limmed 0x3fff,0xffff,iacc0hsmu28: set_gr_limmed 0x8000,0x0000,gr7 ; max positive result set_gr_limmed 0x8000,0x0000,gr8 smu gr7,gr8 test_gr_limmed 0x8000,0x0000,gr8 test_gr_limmed 0x8000,0x0000,gr7 test_spr_immed 0x00000000,iacc0l test_spr_limmed 0x4000,0x0000,iacc0h pass⌨️ 快捷键说明
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