📄 cmqsubhus.cgs

📁 gdb-6.8 Linux下的调试程序最新版本
💻 CGS
字号:
# frv testcase for cmqsubhus $FRi,$FRj,$FRj,$CCi,$cond# mach: frv fr500	.include "../testutils.inc"	start	.global cmqsubhuscmqsubhus:	set_spr_immed	0x1b1b,cccr	set_fr_iimmed	0x0000,0x0000,fr10	set_fr_iimmed	0xdead,0xbeef,fr11	set_fr_iimmed	0x0000,0x0000,fr12	set_fr_iimmed	0x0000,0x0000,fr13	cmqsubhus	fr10,fr12,fr14,cc0,1	test_fr_limmed	0x0000,0x0000,fr14	test_fr_limmed	0xdead,0xbeef,fr15	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear	test_spr_bits	2,1,0,msr0		; msr0.ovf not set	test_spr_bits	1,0,0,msr0		; msr0.aovf not set	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set	set_fr_iimmed	0x1234,0x5678,fr10	set_fr_iimmed	0x7ffe,0x7ffe,fr11	set_fr_iimmed	0x1111,0x1111,fr12	set_fr_iimmed	0x0002,0x0001,fr13	cmqsubhus	fr10,fr12,fr14,cc0,1	test_fr_limmed	0x0123,0x4567,fr14	test_fr_limmed	0x7ffc,0x7ffd,fr15	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear	test_spr_bits	2,1,0,msr0		; msr0.ovf not set	test_spr_bits	1,0,0,msr0		; msr0.aovf not set	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set	set_spr_immed	0,msr0	set_fr_iimmed	0x0001,0x0001,fr10	set_fr_iimmed	0x0001,0x0001,fr11	set_fr_iimmed	0x0001,0x0002,fr12	set_fr_iimmed	0x0002,0x0001,fr13	cmqsubhus	fr10,fr12,fr14,cc4,1	test_fr_limmed	0x0000,0x0000,fr14	test_fr_limmed	0x0000,0x0000,fr15	test_spr_bits	0x3c,2,0x6,msr0		; msr0.sie is set	test_spr_bits	2,1,1,msr0		; msr0.ovf set	test_spr_bits	1,0,1,msr0		; msr0.aovf set	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set	set_spr_immed	0,msr0	set_spr_immed	0,msr1	set_fr_iimmed	0x0001,0x0001,fr10	set_fr_iimmed	0x0002,0x0002,fr11	set_fr_iimmed	0x0000,0x0001,fr12	set_fr_iimmed	0x0002,0x0003,fr13	cmqsubhus.p	fr10,fr10,fr14,cc4,1	cmqsubhus	fr10,fr12,fr16,cc4,1	test_fr_limmed	0x0000,0x0000,fr14	test_fr_limmed	0x0000,0x0000,fr15	test_fr_limmed	0x0001,0x0000,fr16	test_fr_limmed	0x0000,0x0000,fr17	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear	test_spr_bits	2,1,0,msr0		; msr0.ovf not set	test_spr_bits	0x3c,2,0x1,msr1		; msr1.sie is set	test_spr_bits	2,1,1,msr1		; msr1.ovf set	test_spr_bits	1,0,1,msr0		; msr0.aovf set	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set	set_spr_immed	0,msr0	set_spr_immed	0,msr1	set_fr_iimmed	0x0000,0x0000,fr10	set_fr_iimmed	0xdead,0xbeef,fr11	set_fr_iimmed	0x0000,0x0000,fr12	set_fr_iimmed	0x0000,0x0000,fr13	cmqsubhus	fr10,fr12,fr14,cc1,0	test_fr_limmed	0x0000,0x0000,fr14	test_fr_limmed	0xdead,0xbeef,fr15	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear	test_spr_bits	2,1,0,msr0		; msr0.ovf not set	test_spr_bits	1,0,0,msr0		; msr0.aovf not set	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set	set_fr_iimmed	0x1234,0x5678,fr10	set_fr_iimmed	0x7ffe,0x7ffe,fr11	set_fr_iimmed	0x1111,0x1111,fr12	set_fr_iimmed	0x0002,0x0001,fr13	cmqsubhus	fr10,fr12,fr14,cc1,0	test_fr_limmed	0x0123,0x4567,fr14	test_fr_limmed	0x7ffc,0x7ffd,fr15	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear	test_spr_bits	2,1,0,msr0		; msr0.ovf not set	test_spr_bits	1,0,0,msr0		; msr0.aovf not set	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set	set_spr_immed	0,msr0	set_fr_iimmed	0x0001,0x0001,fr10	set_fr_iimmed	0x0001,0x0001,fr11	set_fr_iimmed	0x0001,0x0002,fr12	set_fr_iimmed	0x0002,0x0001,fr13	cmqsubhus	fr10,fr12,fr14,cc5,0	test_fr_limmed	0x0000,0x0000,fr14	test_fr_limmed	0x0000,0x0000,fr15	test_spr_bits	0x3c,2,0x6,msr0		; msr0.sie is set	test_spr_bits	2,1,1,msr0		; msr0.ovf set	test_spr_bits	1,0,1,msr0		; msr0.aovf set	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set	set_spr_immed	0,msr0	set_spr_immed	0,msr1	set_fr_iimmed	0x0001,0x0001,fr10	set_fr_iimmed	0x0002,0x0002,fr11	set_fr_iimmed	0x0000,0x0001,fr12	set_fr_iimmed	0x0002,0x0003,fr13	cmqsubhus.p	fr10,fr10,fr14,cc5,0	cmqsubhus	fr10,fr12,fr16,cc5,0	test_fr_limmed	0x0000,0x0000,fr14	test_fr_limmed	0x0000,0x0000,fr15	test_fr_limmed	0x0001,0x0000,fr16	test_fr_limmed	0x0000,0x0000,fr17	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear	test_spr_bits	2,1,0,msr0		; msr0.ovf not set	test_spr_bits	0x3c,2,0x1,msr1		; msr1.sie is set	test_spr_bits	2,1,1,msr1		; msr1.ovf set	test_spr_bits	1,0,1,msr0		; msr0.aovf set	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set	set_fr_iimmed	0x1111,0x1111,fr14	set_fr_iimmed	0x2222,0x2222,fr15	set_spr_immed	0,msr0	set_spr_immed	0,msr1	set_fr_iimmed	0x0000,0x0000,fr10	set_fr_iimmed	0xdead,0xbeef,fr11	set_fr_iimmed	0x0000,0x0000,fr12	set_fr_iimmed	0x0000,0x0000,fr13	cmqsubhus	fr10,fr12,fr14,cc0,0	test_fr_limmed	0x1111,0x1111,fr14	test_fr_limmed	0x2222,0x2222,fr15	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear	test_spr_bits	2,1,0,msr0		; msr0.ovf not set	test_spr_bits	1,0,0,msr0		; msr0.aovf not set	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set	set_fr_iimmed	0x1234,0x5678,fr10	set_fr_iimmed	0x7ffe,0x7ffe,fr11	set_fr_iimmed	0x1111,0x1111,fr12	set_fr_iimmed	0x0002,0x0001,fr13	cmqsubhus	fr10,fr12,fr14,cc0,0	test_fr_limmed	0x1111,0x1111,fr14	test_fr_limmed	0x2222,0x2222,fr15	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear	test_spr_bits	2,1,0,msr0		; msr0.ovf not set	test_spr_bits	1,0,0,msr0		; msr0.aovf not set	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set	set_spr_immed	0,msr0	set_fr_iimmed	0x0001,0x0001,fr10	set_fr_iimmed	0x0001,0x0001,fr11	set_fr_iimmed	0x0001,0x0002,fr12	set_fr_iimmed	0x0002,0x0001,fr13	cmqsubhus	fr10,fr12,fr14,cc4,0	test_fr_limmed	0x1111,0x1111,fr14	test_fr_limmed	0x2222,0x2222,fr15	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear	test_spr_bits	2,1,0,msr0		; msr0.ovf not set	test_spr_bits	1,0,0,msr0		; msr0.aovf not set	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set	set_fr_iimmed	0x3333,0x3333,fr16	set_fr_iimmed	0x4444,0x4444,fr17	set_spr_immed	0,msr0	set_spr_immed	0,msr1	set_fr_iimmed	0x0001,0x0001,fr10	set_fr_iimmed	0x0002,0x0002,fr11	set_fr_iimmed	0x0000,0x0001,fr12	set_fr_iimmed	0x0002,0x0003,fr13	cmqsubhus.p	fr10,fr10,fr14,cc4,0	cmqsubhus	fr10,fr12,fr16,cc4,0	test_fr_limmed	0x1111,0x1111,fr14	test_fr_limmed	0x2222,0x2222,fr15	test_fr_limmed	0x3333,0x3333,fr16	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear	test_spr_bits	2,1,0,msr0		; msr0.ovf not set	test_spr_bits	2,1,0,msr1		; msr1.ovf not set	test_spr_bits	1,0,0,msr0		; msr0.aovf not set	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set	test_fr_limmed	0x4444,0x4444,fr17	set_fr_iimmed	0x1111,0x1111,fr14	set_fr_iimmed	0x2222,0x2222,fr15	set_spr_immed	0,msr0	set_spr_immed	0,msr1	set_fr_iimmed	0x0000,0x0000,fr10	set_fr_iimmed	0xdead,0xbeef,fr11	set_fr_iimmed	0x0000,0x0000,fr12	set_fr_iimmed	0x0000,0x0000,fr13	cmqsubhus	fr10,fr12,fr14,cc1,1	test_fr_limmed	0x1111,0x1111,fr14	test_fr_limmed	0x2222,0x2222,fr15	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear	test_spr_bits	2,1,0,msr0		; msr0.ovf not set	test_spr_bits	1,0,0,msr0		; msr0.aovf not set	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set	set_fr_iimmed	0x1234,0x5678,fr10	set_fr_iimmed	0x7ffe,0x7ffe,fr11	set_fr_iimmed	0x1111,0x1111,fr12	set_fr_iimmed	0x0002,0x0001,fr13	cmqsubhus	fr10,fr12,fr14,cc1,1	test_fr_limmed	0x1111,0x1111,fr14	test_fr_limmed	0x2222,0x2222,fr15	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear	test_spr_bits	2,1,0,msr0		; msr0.ovf not set	test_spr_bits	1,0,0,msr0		; msr0.aovf not set	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set	set_spr_immed	0,msr0	set_fr_iimmed	0x0001,0x0001,fr10	set_fr_iimmed	0x0001,0x0001,fr11	set_fr_iimmed	0x0001,0x0002,fr12	set_fr_iimmed	0x0002,0x0001,fr13	cmqsubhus	fr10,fr12,fr14,cc5,1	test_fr_limmed	0x1111,0x1111,fr14	test_fr_limmed	0x2222,0x2222,fr15	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear	test_spr_bits	2,1,0,msr0		; msr0.ovf not set	test_spr_bits	1,0,0,msr0		; msr0.aovf not set	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set	set_fr_iimmed	0x3333,0x3333,fr16	set_fr_iimmed	0x4444,0x4444,fr17	set_spr_immed	0,msr0	set_spr_immed	0,msr1	set_fr_iimmed	0x0001,0x0001,fr10	set_fr_iimmed	0x0002,0x0002,fr11	set_fr_iimmed	0x0000,0x0001,fr12	set_fr_iimmed	0x0002,0x0003,fr13	cmqsubhus.p	fr10,fr10,fr14,cc5,1	cmqsubhus	fr10,fr12,fr16,cc5,1	test_fr_limmed	0x1111,0x1111,fr14	test_fr_limmed	0x2222,0x2222,fr15	test_fr_limmed	0x3333,0x3333,fr16	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear	test_spr_bits	2,1,0,msr0		; msr0.ovf not set	test_spr_bits	2,1,0,msr1		; msr1.ovf not set	test_spr_bits	1,0,0,msr0		; msr0.aovf not set	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set	test_fr_limmed	0x4444,0x4444,fr17	set_fr_iimmed	0x1111,0x1111,fr14	set_fr_iimmed	0x2222,0x2222,fr15	set_spr_immed	0,msr0	set_spr_immed	0,msr1	set_fr_iimmed	0x0000,0x0000,fr10	set_fr_iimmed	0xdead,0xbeef,fr11	set_fr_iimmed	0x0000,0x0000,fr12	set_fr_iimmed	0x0000,0x0000,fr13	cmqsubhus	fr10,fr12,fr14,cc2,1	test_fr_limmed	0x1111,0x1111,fr14	test_fr_limmed	0x2222,0x2222,fr15	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear	test_spr_bits	2,1,0,msr0		; msr0.ovf not set	test_spr_bits	1,0,0,msr0		; msr0.aovf not set	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set	set_fr_iimmed	0x1234,0x5678,fr10	set_fr_iimmed	0x7ffe,0x7ffe,fr11	set_fr_iimmed	0x1111,0x1111,fr12	set_fr_iimmed	0x0002,0x0001,fr13	cmqsubhus	fr10,fr12,fr14,cc2,0	test_fr_limmed	0x1111,0x1111,fr14	test_fr_limmed	0x2222,0x2222,fr15	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear	test_spr_bits	2,1,0,msr0		; msr0.ovf not set	test_spr_bits	1,0,0,msr0		; msr0.aovf not set	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set	set_spr_immed	0,msr0	set_fr_iimmed	0x0001,0x0001,fr10	set_fr_iimmed	0x0001,0x0001,fr11	set_fr_iimmed	0x0001,0x0002,fr12	set_fr_iimmed	0x0002,0x0001,fr13	cmqsubhus	fr10,fr12,fr14,cc6,1	test_fr_limmed	0x1111,0x1111,fr14	test_fr_limmed	0x2222,0x2222,fr15	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear	test_spr_bits	2,1,0,msr0		; msr0.ovf not set	test_spr_bits	1,0,0,msr0		; msr0.aovf not set	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set	set_fr_iimmed	0x3333,0x3333,fr16	set_fr_iimmed	0x4444,0x4444,fr17	set_spr_immed	0,msr0	set_spr_immed	0,msr1	set_fr_iimmed	0x0001,0x0001,fr10	set_fr_iimmed	0x0002,0x0002,fr11	set_fr_iimmed	0x0000,0x0001,fr12	set_fr_iimmed	0x0002,0x0003,fr13	cmqsubhus.p	fr10,fr10,fr14,cc6,0	cmqsubhus	fr10,fr12,fr16,cc6,1	test_fr_limmed	0x1111,0x1111,fr14	test_fr_limmed	0x2222,0x2222,fr15	test_fr_limmed	0x3333,0x3333,fr16	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear	test_spr_bits	2,1,0,msr0		; msr0.ovf not set	test_spr_bits	2,1,0,msr1		; msr1.ovf not set	test_spr_bits	1,0,0,msr0		; msr0.aovf not set	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set	test_fr_limmed	0x4444,0x4444,fr17;	set_fr_iimmed	0x1111,0x1111,fr14	set_fr_iimmed	0x2222,0x2222,fr15	set_spr_immed	0,msr0	set_spr_immed	0,msr1	set_fr_iimmed	0x0000,0x0000,fr10	set_fr_iimmed	0xdead,0xbeef,fr11	set_fr_iimmed	0x0000,0x0000,fr12	set_fr_iimmed	0x0000,0x0000,fr13	cmqsubhus	fr10,fr12,fr14,cc3,1	test_fr_limmed	0x1111,0x1111,fr14	test_fr_limmed	0x2222,0x2222,fr15	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear	test_spr_bits	2,1,0,msr0		; msr0.ovf not set	test_spr_bits	1,0,0,msr0		; msr0.aovf not set	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set	set_fr_iimmed	0x1234,0x5678,fr10	set_fr_iimmed	0x7ffe,0x7ffe,fr11	set_fr_iimmed	0x1111,0x1111,fr12	set_fr_iimmed	0x0002,0x0001,fr13	cmqsubhus	fr10,fr12,fr14,cc3,0	test_fr_limmed	0x1111,0x1111,fr14	test_fr_limmed	0x2222,0x2222,fr15	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear	test_spr_bits	2,1,0,msr0		; msr0.ovf not set	test_spr_bits	1,0,0,msr0		; msr0.aovf not set	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set	set_spr_immed	0,msr0	set_fr_iimmed	0x0001,0x0001,fr10	set_fr_iimmed	0x0001,0x0001,fr11	set_fr_iimmed	0x0001,0x0002,fr12	set_fr_iimmed	0x0002,0x0001,fr13	cmqsubhus	fr10,fr12,fr14,cc7,1	test_fr_limmed	0x1111,0x1111,fr14	test_fr_limmed	0x2222,0x2222,fr15	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear	test_spr_bits	2,1,0,msr0		; msr0.ovf not set	test_spr_bits	1,0,0,msr0		; msr0.aovf not set	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set	set_fr_iimmed	0x3333,0x3333,fr16	set_fr_iimmed	0x4444,0x4444,fr17	set_spr_immed	0,msr0	set_spr_immed	0,msr1	set_fr_iimmed	0x0001,0x0001,fr10	set_fr_iimmed	0x0002,0x0002,fr11	set_fr_iimmed	0x0000,0x0001,fr12	set_fr_iimmed	0x0002,0x0003,fr13	cmqsubhus.p	fr10,fr10,fr14,cc7,0	cmqsubhus	fr10,fr12,fr16,cc7,1	test_fr_limmed	0x1111,0x1111,fr14	test_fr_limmed	0x2222,0x2222,fr15	test_fr_limmed	0x3333,0x3333,fr16	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear	test_spr_bits	2,1,0,msr0		; msr0.ovf not set	test_spr_bits	2,1,0,msr1		; msr1.ovf not set	test_spr_bits	1,0,0,msr0		; msr0.aovf not set	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set	test_fr_limmed	0x4444,0x4444,fr17	pass
⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -