📄 nfdcmps.cgs
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test_spr_immed 0,fner0 set_fcc 0xd,0 ; Set mask opposite of expected set_fcc 0xd,1 ; Set mask opposite of expected nfdcmps fr48,fr0,fcc0 test_fcc 0x2,0 test_fcc 0x2,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xd,0 ; Set mask opposite of expected set_fcc 0xd,1 ; Set mask opposite of expected nfdcmps fr48,fr4,fcc0 test_fcc 0x2,0 test_fcc 0x2,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xd,0 ; Set mask opposite of expected set_fcc 0xd,1 ; Set mask opposite of expected nfdcmps fr48,fr8,fcc0 test_fcc 0x2,0 test_fcc 0x2,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xd,0 ; Set mask opposite of expected set_fcc 0xd,1 ; Set mask opposite of expected nfdcmps fr48,fr12,fcc0 test_fcc 0x2,0 test_fcc 0x2,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xd,0 ; Set mask opposite of expected set_fcc 0xd,1 ; Set mask opposite of expected nfdcmps fr48,fr16,fcc0 test_fcc 0x2,0 test_fcc 0x2,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xd,0 ; Set mask opposite of expected set_fcc 0xd,1 ; Set mask opposite of expected nfdcmps fr48,fr20,fcc0 test_fcc 0x2,0 test_fcc 0x2,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xd,0 ; Set mask opposite of expected set_fcc 0xd,1 ; Set mask opposite of expected nfdcmps fr48,fr24,fcc0 test_fcc 0x2,0 test_fcc 0x2,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xd,0 ; Set mask opposite of expected set_fcc 0xd,1 ; Set mask opposite of expected nfdcmps fr48,fr28,fcc0 test_fcc 0x2,0 test_fcc 0x2,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xd,0 ; Set mask opposite of expected set_fcc 0xd,1 ; Set mask opposite of expected nfdcmps fr48,fr32,fcc0 test_fcc 0x2,0 test_fcc 0x2,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xd,0 ; Set mask opposite of expected set_fcc 0xd,1 ; Set mask opposite of expected nfdcmps fr48,fr36,fcc0 test_fcc 0x2,0 test_fcc 0x2,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xd,0 ; Set mask opposite of expected set_fcc 0xd,1 ; Set mask opposite of expected nfdcmps fr48,fr40,fcc0 test_fcc 0x2,0 test_fcc 0x2,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xd,0 ; Set mask opposite of expected set_fcc 0xd,1 ; Set mask opposite of expected nfdcmps fr48,fr44,fcc0 test_fcc 0x2,0 test_fcc 0x2,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0x7,0 ; Set mask opposite of expected set_fcc 0x7,1 ; Set mask opposite of expected nfdcmps fr48,fr48,fcc0 test_fcc 0x8,0 test_fcc 0x8,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr48,fr52,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr48,fr56,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr48,fr60,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xd,0 ; Set mask opposite of expected set_fcc 0xd,1 ; Set mask opposite of expected nfdcmps fr52,fr0,fcc0 test_fcc 0x2,0 test_fcc 0x2,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xd,0 ; Set mask opposite of expected set_fcc 0xd,1 ; Set mask opposite of expected nfdcmps fr52,fr4,fcc0 test_fcc 0x2,0 test_fcc 0x2,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xd,0 ; Set mask opposite of expected set_fcc 0xd,1 ; Set mask opposite of expected nfdcmps fr52,fr8,fcc0 test_fcc 0x2,0 test_fcc 0x2,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xd,0 ; Set mask opposite of expected set_fcc 0xd,1 ; Set mask opposite of expected nfdcmps fr52,fr12,fcc0 test_fcc 0x2,0 test_fcc 0x2,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xd,0 ; Set mask opposite of expected set_fcc 0xd,1 ; Set mask opposite of expected nfdcmps fr52,fr16,fcc0 test_fcc 0x2,0 test_fcc 0x2,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xd,0 ; Set mask opposite of expected set_fcc 0xd,1 ; Set mask opposite of expected nfdcmps fr52,fr20,fcc0 test_fcc 0x2,0 test_fcc 0x2,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xd,0 ; Set mask opposite of expected set_fcc 0xd,1 ; Set mask opposite of expected nfdcmps fr52,fr24,fcc0 test_fcc 0x2,0 test_fcc 0x2,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xd,0 ; Set mask opposite of expected set_fcc 0xd,1 ; Set mask opposite of expected nfdcmps fr52,fr28,fcc0 test_fcc 0x2,0 test_fcc 0x2,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xd,0 ; Set mask opposite of expected set_fcc 0xd,1 ; Set mask opposite of expected nfdcmps fr52,fr32,fcc0 test_fcc 0x2,0 test_fcc 0x2,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xd,0 ; Set mask opposite of expected set_fcc 0xd,1 ; Set mask opposite of expected nfdcmps fr52,fr36,fcc0 test_fcc 0x2,0 test_fcc 0x2,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xd,0 ; Set mask opposite of expected set_fcc 0xd,1 ; Set mask opposite of expected nfdcmps fr52,fr40,fcc0 test_fcc 0x2,0 test_fcc 0x2,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xd,0 ; Set mask opposite of expected set_fcc 0xd,1 ; Set mask opposite of expected nfdcmps fr52,fr44,fcc0 test_fcc 0x2,0 test_fcc 0x2,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xd,0 ; Set mask opposite of expected set_fcc 0xd,1 ; Set mask opposite of expected nfdcmps fr52,fr48,fcc0 test_fcc 0x2,0 test_fcc 0x2,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0x7,0 ; Set mask opposite of expected set_fcc 0x7,1 ; Set mask opposite of expected nfdcmps fr52,fr52,fcc0 test_fcc 0x8,0 test_fcc 0x8,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr52,fr56,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr52,fr60,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr56,fr0,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr56,fr4,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr56,fr8,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr56,fr12,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr56,fr16,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr56,fr20,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr56,fr24,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr56,fr28,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr56,fr32,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr56,fr36,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr56,fr40,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr56,fr44,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr56,fr48,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr56,fr52,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr56,fr56,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr56,fr60,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr60,fr0,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr60,fr4,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr60,fr8,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr60,fr12,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr60,fr16,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr60,fr20,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr60,fr24,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr60,fr28,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr60,fr32,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr60,fr36,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr60,fr40,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr60,fr44,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr60,fr48,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr60,fr52,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr60,fr56,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr60,fr60,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 pass⌨️ 快捷键说明
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