📄 nfdcmps.cgs

📁 gdb-6.8 Linux下的调试程序最新版本
💻 CGS
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	set_fcc         0xe,1		; Set mask opposite of expected	nfdcmps      	fr12,fr60,fcc0	test_fcc	0x1,0	test_fcc	0x1,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xd,0		; Set mask opposite of expected	set_fcc         0xd,1		; Set mask opposite of expected	nfdcmps      	fr16,fr0,fcc0	test_fcc	0x2,0	test_fcc	0x2,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xd,0		; Set mask opposite of expected	set_fcc         0xd,1		; Set mask opposite of expected	nfdcmps      	fr16,fr4,fcc0	test_fcc	0x2,0	test_fcc	0x2,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xd,0		; Set mask opposite of expected	set_fcc         0xd,1		; Set mask opposite of expected	nfdcmps      	fr16,fr8,fcc0	test_fcc	0x2,0	test_fcc	0x2,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xd,0		; Set mask opposite of expected	set_fcc         0xd,1		; Set mask opposite of expected	nfdcmps      	fr16,fr12,fcc0	test_fcc	0x2,0	test_fcc	0x2,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0x7,0		; Set mask opposite of expected	set_fcc         0x7,1		; Set mask opposite of expected	nfdcmps      	fr16,fr16,fcc0	test_fcc	0x8,0	test_fcc	0x8,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0x7,0		; Set mask opposite of expected	set_fcc         0x7,1		; Set mask opposite of expected	nfdcmps      	fr16,fr20,fcc0	test_fcc	0x8,0	test_fcc	0x8,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xb,0		; Set mask opposite of expected	set_fcc         0xb,1		; Set mask opposite of expected	nfdcmps      	fr16,fr24,fcc0	test_fcc	0x4,0	test_fcc	0x4,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xb,0		; Set mask opposite of expected	set_fcc         0xb,1		; Set mask opposite of expected	nfdcmps      	fr16,fr28,fcc0	test_fcc	0x4,0	test_fcc	0x4,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xb,0		; Set mask opposite of expected	set_fcc         0xb,1		; Set mask opposite of expected	nfdcmps      	fr16,fr32,fcc0	test_fcc	0x4,0	test_fcc	0x4,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xb,0		; Set mask opposite of expected	set_fcc         0xb,1		; Set mask opposite of expected	nfdcmps      	fr16,fr36,fcc0	test_fcc	0x4,0	test_fcc	0x4,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xb,0		; Set mask opposite of expected	set_fcc         0xb,1		; Set mask opposite of expected	nfdcmps      	fr16,fr40,fcc0	test_fcc	0x4,0	test_fcc	0x4,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xb,0		; Set mask opposite of expected	set_fcc         0xb,1		; Set mask opposite of expected	nfdcmps      	fr16,fr44,fcc0	test_fcc	0x4,0	test_fcc	0x4,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xb,0		; Set mask opposite of expected	set_fcc         0xb,1		; Set mask opposite of expected	nfdcmps      	fr16,fr48,fcc0	test_fcc	0x4,0	test_fcc	0x4,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xb,0		; Set mask opposite of expected	set_fcc         0xb,1		; Set mask opposite of expected	nfdcmps      	fr16,fr52,fcc0	test_fcc	0x4,0	test_fcc	0x4,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xe,0		; Set mask opposite of expected	set_fcc         0xe,1		; Set mask opposite of expected	nfdcmps      	fr16,fr56,fcc0	test_fcc	0x1,0	test_fcc	0x1,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xe,0		; Set mask opposite of expected	set_fcc         0xe,1		; Set mask opposite of expected	nfdcmps      	fr16,fr60,fcc0	test_fcc	0x1,0	test_fcc	0x1,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xd,0		; Set mask opposite of expected	set_fcc         0xd,1		; Set mask opposite of expected	nfdcmps      	fr20,fr0,fcc0	test_fcc	0x2,0	test_fcc	0x2,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xd,0		; Set mask opposite of expected	set_fcc         0xd,1		; Set mask opposite of expected	nfdcmps      	fr20,fr4,fcc0	test_fcc	0x2,0	test_fcc	0x2,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xd,0		; Set mask opposite of expected	set_fcc         0xd,1		; Set mask opposite of expected	nfdcmps      	fr20,fr8,fcc0	test_fcc	0x2,0	test_fcc	0x2,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xd,0		; Set mask opposite of expected	set_fcc         0xd,1		; Set mask opposite of expected	nfdcmps      	fr20,fr12,fcc0	test_fcc	0x2,0	test_fcc	0x2,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0x7,0		; Set mask opposite of expected	set_fcc         0x7,1		; Set mask opposite of expected	nfdcmps      	fr20,fr16,fcc0	test_fcc	0x8,0	test_fcc	0x8,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0x7,0		; Set mask opposite of expected	set_fcc         0x7,1		; Set mask opposite of expected	nfdcmps      	fr20,fr20,fcc0	test_fcc	0x8,0	test_fcc	0x8,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xb,0		; Set mask opposite of expected	set_fcc         0xb,1		; Set mask opposite of expected	nfdcmps      	fr20,fr24,fcc0	test_fcc	0x4,0	test_fcc	0x4,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xb,0		; Set mask opposite of expected	set_fcc         0xb,1		; Set mask opposite of expected	nfdcmps      	fr20,fr28,fcc0	test_fcc	0x4,0	test_fcc	0x4,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xb,0		; Set mask opposite of expected	set_fcc         0xb,1		; Set mask opposite of expected	nfdcmps      	fr20,fr32,fcc0	test_fcc	0x4,0	test_fcc	0x4,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xb,0		; Set mask opposite of expected	set_fcc         0xb,1		; Set mask opposite of expected	nfdcmps      	fr20,fr36,fcc0	test_fcc	0x4,0	test_fcc	0x4,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xb,0		; Set mask opposite of expected	set_fcc         0xb,1		; Set mask opposite of expected	nfdcmps      	fr20,fr40,fcc0	test_fcc	0x4,0	test_fcc	0x4,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xb,0		; Set mask opposite of expected	set_fcc         0xb,1		; Set mask opposite of expected	nfdcmps      	fr20,fr44,fcc0	test_fcc	0x4,0	test_fcc	0x4,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xb,0		; Set mask opposite of expected	set_fcc         0xb,1		; Set mask opposite of expected	nfdcmps      	fr20,fr48,fcc0	test_fcc	0x4,0	test_fcc	0x4,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xb,0		; Set mask opposite of expected	set_fcc         0xb,1		; Set mask opposite of expected	nfdcmps      	fr20,fr52,fcc0	test_fcc	0x4,0	test_fcc	0x4,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xe,0		; Set mask opposite of expected	set_fcc         0xe,1		; Set mask opposite of expected	nfdcmps      	fr20,fr56,fcc0	test_fcc	0x1,0	test_fcc	0x1,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xe,0		; Set mask opposite of expected	set_fcc         0xe,1		; Set mask opposite of expected	nfdcmps      	fr20,fr60,fcc0	test_fcc	0x1,0	test_fcc	0x1,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xd,0		; Set mask opposite of expected	set_fcc         0xd,1		; Set mask opposite of expected	nfdcmps      	fr24,fr0,fcc0	test_fcc	0x2,0	test_fcc	0x2,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xd,0		; Set mask opposite of expected	set_fcc         0xd,1		; Set mask opposite of expected	nfdcmps      	fr24,fr4,fcc0	test_fcc	0x2,0	test_fcc	0x2,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xd,0		; Set mask opposite of expected	set_fcc         0xd,1		; Set mask opposite of expected	nfdcmps      	fr24,fr8,fcc0	test_fcc	0x2,0	test_fcc	0x2,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xd,0		; Set mask opposite of expected	set_fcc         0xd,1		; Set mask opposite of expected	nfdcmps      	fr24,fr12,fcc0	test_fcc	0x2,0	test_fcc	0x2,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xd,0		; Set mask opposite of expected	set_fcc         0xd,1		; Set mask opposite of expected	nfdcmps      	fr24,fr16,fcc0	test_fcc	0x2,0	test_fcc	0x2,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xd,0		; Set mask opposite of expected	set_fcc         0xd,1		; Set mask opposite of expected	nfdcmps      	fr24,fr20,fcc0	test_fcc	0x2,0	test_fcc	0x2,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0x7,0		; Set mask opposite of expected	set_fcc         0x7,1		; Set mask opposite of expected	nfdcmps      	fr24,fr24,fcc0	test_fcc	0x8,0	test_fcc	0x8,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xb,0		; Set mask opposite of expected	set_fcc         0xb,1		; Set mask opposite of expected	nfdcmps      	fr24,fr28,fcc0	test_fcc	0x4,0	test_fcc	0x4,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xb,0		; Set mask opposite of expected	set_fcc         0xb,1		; Set mask opposite of expected	nfdcmps      	fr24,fr32,fcc0	test_fcc	0x4,0	test_fcc	0x4,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xb,0		; Set mask opposite of expected	set_fcc         0xb,1		; Set mask opposite of expected	nfdcmps      	fr24,fr36,fcc0	test_fcc	0x4,0	test_fcc	0x4,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xb,0		; Set mask opposite of expected	set_fcc         0xb,1		; Set mask opposite of expected	nfdcmps      	fr24,fr40,fcc0	test_fcc	0x4,0	test_fcc	0x4,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xb,0		; Set mask opposite of expected	set_fcc         0xb,1		; Set mask opposite of expected	nfdcmps      	fr24,fr44,fcc0	test_fcc	0x4,0	test_fcc	0x4,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xb,0		; Set mask opposite of expected	set_fcc         0xb,1		; Set mask opposite of expected	nfdcmps      	fr24,fr48,fcc0	test_fcc	0x4,0	test_fcc	0x4,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xb,0		; Set mask opposite of expected	set_fcc         0xb,1		; Set mask opposite of expected	nfdcmps      	fr24,fr52,fcc0	test_fcc	0x4,0	test_fcc	0x4,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xe,0		; Set mask opposite of expected	set_fcc         0xe,1		; Set mask opposite of expected	nfdcmps      	fr24,fr56,fcc0	test_fcc	0x1,0	test_fcc	0x1,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xe,0		; Set mask opposite of expected	set_fcc         0xe,1		; Set mask opposite of expected	nfdcmps      	fr24,fr60,fcc0	test_fcc	0x1,0	test_fcc	0x1,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xd,0		; Set mask opposite of expected	set_fcc         0xd,1		; Set mask opposite of expected	nfdcmps      	fr28,fr0,fcc0	test_fcc	0x2,0	test_fcc	0x2,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xd,0		; Set mask opposite of expected	set_fcc         0xd,1		; Set mask opposite of expected	nfdcmps      	fr28,fr4,fcc0	test_fcc	0x2,0	test_fcc	0x2,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xd,0		; Set mask opposite of expected	set_fcc         0xd,1		; Set mask opposite of expected	nfdcmps      	fr28,fr8,fcc0	test_fcc	0x2,0	test_fcc	0x2,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xd,0		; Set mask opposite of expected	set_fcc         0xd,1		; Set mask opposite of expected	nfdcmps      	fr28,fr12,fcc0	test_fcc	0x2,0	test_fcc	0x2,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xd,0		; Set mask opposite of expected	set_fcc         0xd,1		; Set mask opposite of expected	nfdcmps      	fr28,fr16,fcc0	test_fcc	0x2,0	test_fcc	0x2,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xd,0		; Set mask opposite of expected	set_fcc         0xd,1		; Set mask opposite of expected	nfdcmps      	fr28,fr20,fcc0	test_fcc	0x2,0	test_fcc	0x2,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xd,0		; Set mask opposite of expected	set_fcc         0xd,1		; Set mask opposite of expected	nfdcmps      	fr28,fr24,fcc0	test_fcc	0x2,0	test_fcc	0x2,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0x7,0		; Set mask opposite of expected	set_fcc         0x7,1		; Set mask opposite of expected	nfdcmps      	fr28,fr28,fcc0	test_fcc	0x8,0	test_fcc	0x8,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xb,0		; Set mask opposite of expected	set_fcc         0xb,1		; Set mask opposite of expected	nfdcmps      	fr28,fr32,fcc0	test_fcc	0x4,0	test_fcc	0x4,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xb,0		; Set mask opposite of expected	set_fcc         0xb,1		; Set mask opposite of expected	nfdcmps      	fr28,fr36,fcc0	test_fcc	0x4,0	test_fcc	0x4,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xb,0		; Set mask opposite of expected	set_fcc         0xb,1		; Set mask opposite of expected	nfdcmps      	fr28,fr40,fcc0	test_fcc	0x4,0	test_fcc	0x4,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xb,0		; Set mask opposite of expected	set_fcc         0xb,1		; Set mask opposite of expected	nfdcmps      	fr28,fr44,fcc0	test_fcc	0x4,0	test_fcc	0x4,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xb,0		; Set mask opposite of expected	set_fcc         0xb,1		; Set mask opposite of expected	nfdcmps      	fr28,fr48,fcc0	test_fcc	0x4,0	test_fcc	0x4,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xb,0		; Set mask opposite of expected	set_fcc         0xb,1		; Set mask opposite of expected	nfdcmps      	fr28,fr52,fcc0	test_fcc	0x4,0	test_fcc	0x4,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xe,0		; Set mask opposite of expected	set_fcc         0xe,1		; Set mask opposite of expected	nfdcmps      	fr28,fr56,fcc0	test_fcc	0x1,0	test_fcc	0x1,1	test_spr_immed	0,fner1	test_spr_immed	0,fner0	set_fcc         0xe,0		; Set mask opposite of expected	set_fcc         0xe,1		; Set mask opposite of expected	nfdcmps      	fr28,fr60,fcc0	test_fcc	0x1,0	test_fcc	0x1,1	test_spr_immed	0,fner1
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