📄 nfdcmps.cgs
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# frv testcase for nfdcmps $FRi,$FRj,$FCCi_2# mach: frv .include "testutils.inc" float_constants start load_float_constants load_float_constants1 .global nfdcmpsnfdcmps: set_fcc 0x7,0 ; Set mask opposite of expected set_fcc 0x7,1 ; Set mask opposite of expected nfdcmps fr0,fr0,fcc0 test_fcc 0x8,0 test_fcc 0x8,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr0,fr4,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr0,fr8,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr0,fr12,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr0,fr16,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr0,fr20,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr0,fr24,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr0,fr28,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr0,fr32,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr0,fr36,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr0,fr40,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr0,fr44,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr0,fr48,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr0,fr52,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr0,fr56,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr0,fr60,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xd,0 ; Set mask opposite of expected set_fcc 0xd,1 ; Set mask opposite of expected nfdcmps fr4,fr0,fcc0 test_fcc 0x2,0 test_fcc 0x2,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0x7,0 ; Set mask opposite of expected set_fcc 0x7,1 ; Set mask opposite of expected nfdcmps fr4,fr4,fcc0 test_fcc 0x8,0 test_fcc 0x8,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr4,fr8,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr4,fr12,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr4,fr16,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr4,fr20,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr4,fr24,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr4,fr28,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr4,fr32,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr4,fr36,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr4,fr40,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr4,fr44,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr4,fr48,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr4,fr52,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr4,fr56,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr4,fr60,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xd,0 ; Set mask opposite of expected set_fcc 0xd,1 ; Set mask opposite of expected nfdcmps fr8,fr0,fcc0 test_fcc 0x2,0 test_fcc 0x2,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xd,0 ; Set mask opposite of expected set_fcc 0xd,1 ; Set mask opposite of expected nfdcmps fr8,fr4,fcc0 test_fcc 0x2,0 test_fcc 0x2,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0x7,0 ; Set mask opposite of expected set_fcc 0x7,1 ; Set mask opposite of expected nfdcmps fr8,fr8,fcc0 test_fcc 0x8,0 test_fcc 0x8,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr8,fr12,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr8,fr16,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr8,fr20,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr8,fr24,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr8,fr28,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr8,fr32,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr8,fr36,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr8,fr40,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr8,fr44,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr8,fr48,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr8,fr52,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr8,fr56,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr8,fr60,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xd,0 ; Set mask opposite of expected set_fcc 0xd,1 ; Set mask opposite of expected nfdcmps fr12,fr0,fcc0 test_fcc 0x2,0 test_fcc 0x2,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xd,0 ; Set mask opposite of expected set_fcc 0xd,1 ; Set mask opposite of expected nfdcmps fr12,fr4,fcc0 test_fcc 0x2,0 test_fcc 0x2,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xd,0 ; Set mask opposite of expected set_fcc 0xd,1 ; Set mask opposite of expected nfdcmps fr12,fr8,fcc0 test_fcc 0x2,0 test_fcc 0x2,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0x7,0 ; Set mask opposite of expected set_fcc 0x7,1 ; Set mask opposite of expected nfdcmps fr12,fr12,fcc0 test_fcc 0x8,0 test_fcc 0x8,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr12,fr16,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr12,fr20,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr12,fr24,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr12,fr28,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr12,fr32,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr12,fr36,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr12,fr40,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr12,fr44,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr12,fr48,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xb,0 ; Set mask opposite of expected set_fcc 0xb,1 ; Set mask opposite of expected nfdcmps fr12,fr52,fcc0 test_fcc 0x4,0 test_fcc 0x4,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected set_fcc 0xe,1 ; Set mask opposite of expected nfdcmps fr12,fr56,fcc0 test_fcc 0x1,0 test_fcc 0x1,1 test_spr_immed 0,fner1 test_spr_immed 0,fner0 set_fcc 0xe,0 ; Set mask opposite of expected⌨️ 快捷键说明
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