📄 fcbltlr.cgs
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# frv testcase for fcbltlr $FCCi,$ccond,$hint# mach: all .include "testutils.inc" start .global fcbltlrfcbltlr: ; ccond is true set_spr_immed 128,lcr set_spr_addr bad,lr set_fcc 0x0 0 fcbltlr fcc0,0,0 set_spr_addr bad,lr set_fcc 0x1 1 fcbltlr fcc1,0,1 set_spr_addr bad,lr set_fcc 0x2 2 fcbltlr fcc2,0,2 set_spr_addr bad,lr set_fcc 0x3 3 fcbltlr fcc3,0,3 set_spr_addr ok5,lr set_fcc 0x4 0 fcbltlr fcc0,0,0 failok5: set_spr_addr ok6,lr set_fcc 0x5 1 fcbltlr fcc1,0,1 failok6: set_spr_addr ok7,lr set_fcc 0x6 2 fcbltlr fcc2,0,2 failok7: set_spr_addr ok8,lr set_fcc 0x7 3 fcbltlr fcc3,0,3 failok8: set_spr_addr bad,lr set_fcc 0x8 0 fcbltlr fcc0,0,0 set_spr_addr bad,lr set_fcc 0x9 1 fcbltlr fcc1,0,1 set_spr_addr bad,lr set_fcc 0xa 2 fcbltlr fcc2,0,2 set_spr_addr bad,lr set_fcc 0xb 3 fcbltlr fcc3,0,3 set_spr_addr okd,lr set_fcc 0xc 0 fcbltlr fcc0,0,0 failokd: set_spr_addr oke,lr set_fcc 0xd 1 fcbltlr fcc1,0,1 failoke: set_spr_addr okf,lr set_fcc 0xe 2 fcbltlr fcc2,0,2 failokf: set_spr_addr okg,lr set_fcc 0xf 3 fcbltlr fcc3,0,3 failokg: ; ccond is true set_spr_immed 1,lcr set_spr_addr bad,lr set_fcc 0x0 0 fcbltlr fcc0,1,0 set_spr_immed 1,lcr set_spr_addr bad,lr set_fcc 0x1 1 fcbltlr fcc1,1,1 set_spr_immed 1,lcr set_spr_addr bad,lr set_fcc 0x2 2 fcbltlr fcc2,1,2 set_spr_immed 1,lcr set_spr_addr bad,lr set_fcc 0x3 3 fcbltlr fcc3,1,3 set_spr_immed 1,lcr set_spr_addr okl,lr set_fcc 0x4 0 fcbltlr fcc0,1,0 failokl: set_spr_immed 1,lcr set_spr_addr okm,lr set_fcc 0x5 1 fcbltlr fcc1,1,1 failokm: set_spr_immed 1,lcr set_spr_addr okn,lr set_fcc 0x6 2 fcbltlr fcc2,1,2 failokn: set_spr_immed 1,lcr set_spr_addr oko,lr set_fcc 0x7 3 fcbltlr fcc3,1,3 failoko: set_spr_immed 1,lcr set_spr_addr bad,lr set_fcc 0x8 0 fcbltlr fcc0,1,0 set_spr_immed 1,lcr set_spr_addr bad,lr set_fcc 0x9 1 fcbltlr fcc1,1,1 set_spr_immed 1,lcr set_spr_addr bad,lr set_fcc 0xa 2 fcbltlr fcc2,1,2 set_spr_immed 1,lcr set_spr_addr bad,lr set_fcc 0xb 3 fcbltlr fcc3,1,3 set_spr_immed 1,lcr set_spr_addr okt,lr set_fcc 0xc 0 fcbltlr fcc0,1,0 failokt: set_spr_immed 1,lcr set_spr_addr oku,lr set_fcc 0xd 1 fcbltlr fcc1,1,1 failoku: set_spr_immed 1,lcr set_spr_addr okv,lr set_fcc 0xe 2 fcbltlr fcc2,1,2 failokv: set_spr_immed 1,lcr set_spr_addr okw,lr set_fcc 0xf 3 fcbltlr fcc3,1,3 failokw: ; ccond is false set_spr_immed 128,lcr set_fcc 0x0 0 fcbltlr fcc0,1,0 set_fcc 0x1 1 fcbltlr fcc1,1,1 set_fcc 0x2 2 fcbltlr fcc2,1,2 set_fcc 0x3 3 fcbltlr fcc3,1,3 set_fcc 0x4 0 fcbltlr fcc0,1,0 set_fcc 0x5 1 fcbltlr fcc1,1,1 set_fcc 0x6 2 fcbltlr fcc2,1,2 set_fcc 0x7 3 fcbltlr fcc3,1,3 set_fcc 0x8 0 fcbltlr fcc0,1,0 set_fcc 0x9 1 fcbltlr fcc1,1,1 set_fcc 0xa 2 fcbltlr fcc2,1,2 set_fcc 0xb 3 fcbltlr fcc3,1,3 set_fcc 0xc 0 fcbltlr fcc0,1,0 set_fcc 0xd 1 fcbltlr fcc1,1,1 set_fcc 0xe 2 fcbltlr fcc2,1,2 set_fcc 0xf 3 fcbltlr fcc3,1,3 ; ccond is false set_spr_immed 1,lcr set_fcc 0x0 0 fcbltlr fcc0,0,0 set_spr_immed 1,lcr set_fcc 0x1 1 fcbltlr fcc1,0,1 set_spr_immed 1,lcr set_fcc 0x2 2 fcbltlr fcc2,0,2 set_spr_immed 1,lcr set_fcc 0x3 3 fcbltlr fcc3,0,3 set_spr_immed 1,lcr set_fcc 0x4 0 fcbltlr fcc0,0,0 set_spr_immed 1,lcr set_fcc 0x5 1 fcbltlr fcc1,0,1 set_spr_immed 1,lcr set_fcc 0x6 2 fcbltlr fcc2,0,2 set_spr_immed 1,lcr set_fcc 0x7 3 fcbltlr fcc3,0,3 set_spr_immed 1,lcr set_fcc 0x8 0 fcbltlr fcc0,0,0 set_spr_immed 1,lcr set_fcc 0x9 1 fcbltlr fcc1,0,1 set_spr_immed 1,lcr set_fcc 0xa 2 fcbltlr fcc2,0,2 set_spr_immed 1,lcr set_fcc 0xb 3 fcbltlr fcc3,0,3 set_spr_immed 1,lcr set_fcc 0xc 0 fcbltlr fcc0,0,0 set_spr_immed 1,lcr set_fcc 0xd 1 fcbltlr fcc1,0,1 set_spr_immed 1,lcr set_fcc 0xe 2 fcbltlr fcc2,0,2 set_spr_immed 1,lcr set_fcc 0xf 3 fcbltlr fcc3,0,3 passbad: fail⌨️ 快捷键说明
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