📄 cfcmps.cgs

📁 gdb-6.8 Linux下的调试程序最新版本
💻 CGS
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	cfcmps      	fr56,fr56,fcc0,cc5,0	test_fcc	0x1,0	set_fcc         0xe,0		; Set mask opposite of expected	cfcmps      	fr56,fr60,fcc0,cc5,0	test_fcc	0x1,0	set_fcc         0xe,0		; Set mask opposite of expected	cfcmps      	fr60,fr0,fcc0,cc5,0	test_fcc	0x1,0	set_fcc         0xe,0		; Set mask opposite of expected	cfcmps      	fr60,fr4,fcc0,cc5,0	test_fcc	0x1,0	set_fcc         0xe,0		; Set mask opposite of expected	cfcmps      	fr60,fr8,fcc0,cc5,0	test_fcc	0x1,0	set_fcc         0xe,0		; Set mask opposite of expected	cfcmps      	fr60,fr12,fcc0,cc5,0	test_fcc	0x1,0	set_fcc         0xe,0		; Set mask opposite of expected	cfcmps      	fr60,fr16,fcc0,cc5,0	test_fcc	0x1,0	set_fcc         0xe,0		; Set mask opposite of expected	cfcmps      	fr60,fr20,fcc0,cc5,0	test_fcc	0x1,0	set_fcc         0xe,0		; Set mask opposite of expected	cfcmps      	fr60,fr24,fcc0,cc5,0	test_fcc	0x1,0	set_fcc         0xe,0		; Set mask opposite of expected	cfcmps      	fr60,fr28,fcc0,cc5,0	test_fcc	0x1,0	set_fcc         0xe,0		; Set mask opposite of expected	cfcmps      	fr60,fr32,fcc0,cc5,0	test_fcc	0x1,0	set_fcc         0xe,0		; Set mask opposite of expected	cfcmps      	fr60,fr36,fcc0,cc5,0	test_fcc	0x1,0	set_fcc         0xe,0		; Set mask opposite of expected	cfcmps      	fr60,fr40,fcc0,cc5,0	test_fcc	0x1,0	set_fcc         0xe,0		; Set mask opposite of expected	cfcmps      	fr60,fr44,fcc0,cc5,0	test_fcc	0x1,0	set_fcc         0xe,0		; Set mask opposite of expected	cfcmps      	fr60,fr48,fcc0,cc5,0	test_fcc	0x1,0	set_fcc         0xe,0		; Set mask opposite of expected	cfcmps      	fr60,fr52,fcc0,cc5,0	test_fcc	0x1,0	set_fcc         0xe,0		; Set mask opposite of expected	cfcmps      	fr60,fr56,fcc0,cc5,0	test_fcc	0x1,0	set_fcc         0xe,0		; Set mask opposite of expected	cfcmps      	fr60,fr60,fcc0,cc5,0	test_fcc	0x1,0;	set_fcc         0x7,0		; Set mask opposite of expected	cfcmps      	fr0,fr0,fcc0,cc0,0	test_fcc	0x7,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr0,fr4,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr0,fr8,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr0,fr12,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr0,fr16,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr0,fr20,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr0,fr24,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr0,fr28,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr0,fr32,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr0,fr36,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr0,fr40,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr0,fr44,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr0,fr48,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr0,fr52,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xe,0		; Set mask opposite of expected	cfcmps      	fr0,fr56,fcc0,cc0,0	test_fcc	0xe,0	set_fcc         0xe,0		; Set mask opposite of expected	cfcmps      	fr0,fr60,fcc0,cc0,0	test_fcc	0xe,0	set_fcc         0xd,0		; Set mask opposite of expected	cfcmps      	fr4,fr0,fcc0,cc0,0	test_fcc	0xd,0	set_fcc         0x7,0		; Set mask opposite of expected	cfcmps      	fr4,fr4,fcc0,cc0,0	test_fcc	0x7,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr4,fr8,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr4,fr12,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr4,fr16,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr4,fr20,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr4,fr24,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr4,fr28,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr4,fr32,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr4,fr36,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr4,fr40,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr4,fr44,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr4,fr48,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr4,fr52,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xe,0		; Set mask opposite of expected	cfcmps      	fr4,fr56,fcc0,cc0,0	test_fcc	0xe,0	set_fcc         0xe,0		; Set mask opposite of expected	cfcmps      	fr4,fr60,fcc0,cc0,0	test_fcc	0xe,0	set_fcc         0xd,0		; Set mask opposite of expected	cfcmps      	fr8,fr0,fcc0,cc0,0	test_fcc	0xd,0	set_fcc         0xd,0		; Set mask opposite of expected	cfcmps      	fr8,fr4,fcc0,cc0,0	test_fcc	0xd,0	set_fcc         0x7,0		; Set mask opposite of expected	cfcmps      	fr8,fr8,fcc0,cc0,0	test_fcc	0x7,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr8,fr12,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr8,fr16,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr8,fr20,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr8,fr24,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr8,fr28,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr8,fr32,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr8,fr36,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr8,fr40,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr8,fr44,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr8,fr48,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr8,fr52,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xe,0		; Set mask opposite of expected	cfcmps      	fr8,fr56,fcc0,cc0,0	test_fcc	0xe,0	set_fcc         0xe,0		; Set mask opposite of expected	cfcmps      	fr8,fr60,fcc0,cc0,0	test_fcc	0xe,0	set_fcc         0xd,0		; Set mask opposite of expected	cfcmps      	fr12,fr0,fcc0,cc0,0	test_fcc	0xd,0	set_fcc         0xd,0		; Set mask opposite of expected	cfcmps      	fr12,fr4,fcc0,cc0,0	test_fcc	0xd,0	set_fcc         0xd,0		; Set mask opposite of expected	cfcmps      	fr12,fr8,fcc0,cc0,0	test_fcc	0xd,0	set_fcc         0x7,0		; Set mask opposite of expected	cfcmps      	fr12,fr12,fcc0,cc0,0	test_fcc	0x7,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr12,fr16,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr12,fr20,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr12,fr24,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr12,fr28,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr12,fr32,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr12,fr36,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr12,fr40,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr12,fr44,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr12,fr48,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr12,fr52,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xe,0		; Set mask opposite of expected	cfcmps      	fr12,fr56,fcc0,cc0,0	test_fcc	0xe,0	set_fcc         0xe,0		; Set mask opposite of expected	cfcmps      	fr12,fr60,fcc0,cc0,0	test_fcc	0xe,0	set_fcc         0xd,0		; Set mask opposite of expected	cfcmps      	fr16,fr0,fcc0,cc0,0	test_fcc	0xd,0	set_fcc         0xd,0		; Set mask opposite of expected	cfcmps      	fr16,fr4,fcc0,cc0,0	test_fcc	0xd,0	set_fcc         0xd,0		; Set mask opposite of expected	cfcmps      	fr16,fr8,fcc0,cc0,0	test_fcc	0xd,0	set_fcc         0xd,0		; Set mask opposite of expected	cfcmps      	fr16,fr12,fcc0,cc0,0	test_fcc	0xd,0	set_fcc         0x7,0		; Set mask opposite of expected	cfcmps      	fr16,fr16,fcc0,cc0,0	test_fcc	0x7,0	set_fcc         0x7,0		; Set mask opposite of expected	cfcmps      	fr16,fr20,fcc0,cc0,0	test_fcc	0x7,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr16,fr24,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr16,fr28,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr16,fr32,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr16,fr36,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr16,fr40,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr16,fr44,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr16,fr48,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr16,fr52,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xe,0		; Set mask opposite of expected	cfcmps      	fr16,fr56,fcc0,cc0,0	test_fcc	0xe,0	set_fcc         0xe,0		; Set mask opposite of expected	cfcmps      	fr16,fr60,fcc0,cc0,0	test_fcc	0xe,0	set_fcc         0xd,0		; Set mask opposite of expected	cfcmps      	fr20,fr0,fcc0,cc0,0	test_fcc	0xd,0	set_fcc         0xd,0		; Set mask opposite of expected	cfcmps      	fr20,fr4,fcc0,cc0,0	test_fcc	0xd,0	set_fcc         0xd,0		; Set mask opposite of expected	cfcmps      	fr20,fr8,fcc0,cc0,0	test_fcc	0xd,0	set_fcc         0xd,0		; Set mask opposite of expected	cfcmps      	fr20,fr12,fcc0,cc0,0	test_fcc	0xd,0	set_fcc         0x7,0		; Set mask opposite of expected	cfcmps      	fr20,fr16,fcc0,cc0,0	test_fcc	0x7,0	set_fcc         0x7,0		; Set mask opposite of expected	cfcmps      	fr20,fr20,fcc0,cc0,0	test_fcc	0x7,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr20,fr24,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr20,fr28,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr20,fr32,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr20,fr36,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr20,fr40,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr20,fr44,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr20,fr48,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr20,fr52,fcc0,cc0,0	test_fcc	0xb,0	set_fcc         0xe,0		; Set mask opposite of expected	cfcmps      	fr20,fr56,fcc0,cc0,0	test_fcc	0xe,0	set_fcc         0xe,0		; Set mask opposite of expected	cfcmps      	fr20,fr60,fcc0,cc0,0	test_fcc	0xe,0	set_fcc         0xd,0		; Set mask opposite of expected	cfcmps      	fr24,fr0,fcc0,cc4,0	test_fcc	0xd,0	set_fcc         0xd,0		; Set mask opposite of expected	cfcmps      	fr24,fr4,fcc0,cc4,0	test_fcc	0xd,0	set_fcc         0xd,0		; Set mask opposite of expected	cfcmps      	fr24,fr8,fcc0,cc4,0	test_fcc	0xd,0	set_fcc         0xd,0		; Set mask opposite of expected	cfcmps      	fr24,fr12,fcc0,cc4,0	test_fcc	0xd,0	set_fcc         0xd,0		; Set mask opposite of expected	cfcmps      	fr24,fr16,fcc0,cc4,0	test_fcc	0xd,0	set_fcc         0xd,0		; Set mask opposite of expected	cfcmps      	fr24,fr20,fcc0,cc4,0	test_fcc	0xd,0	set_fcc         0x7,0		; Set mask opposite of expected	cfcmps      	fr24,fr24,fcc0,cc4,0	test_fcc	0x7,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr24,fr28,fcc0,cc4,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr24,fr32,fcc0,cc4,0	test_fcc	0xb,0	set_fcc         0xb,0		; Set mask opposite of expected	cfcmps      	fr24,fr36,fcc0,cc4,0
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