mem.h

最新DSP+ARM双核CPU处理器使用的X-loader源程序

/*
 * (C) Copyright 2006
 * Texas Instruments, <www.ti.com>
 * Richard Woodruff <[e-mail]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef _OMAP34XX_MEM_H_
#define _OMAP34XX_MEM_H_

#define SDRC_CS0_OSET    0x0
#define SDRC_CS1_OSET    0x30  /* mirror CS1 regs appear offset 0x30 from CS0 */

#ifndef __ASSEMBLY__

typedef enum {
	STACKED		= 0,
	IP_DDR		= 1,
	COMBO_DDR	= 2,
	IP_SDR	 	= 3,
} mem_t;


/* Memory that can be connected to GPMC */
#define GPMC_NOR            0
#define GPMC_NAND           1
#define GPMC_MDOC           2
#define GPMC_ONENAND        3
#define MMC_NAND			4
#define MMC_ONENAND			5

#endif

/* set the 343x-SDRC incoming address convention */
#if defined(SDRC_B_R_C)
#define B_ALL	(0 << 6)	/* bank-row-column */
#elif defined(SDRC_B1_R_B0_C)
#define B_ALL	(1 << 6)	/* bank1-row-bank0-column */
#elif defined(SDRC_R_B_C)
#define B_ALL	(2 << 6)	/* row-bank-column */
#endif

/* Future memory combinations based on past */
#define SDP_SDRC_MDCFG_MONO_DDR    0x0
#define SDP_COMBO_MDCFG_0_DDR      0x0
#define SDP_SDRC_MDCFG_0_SDR       0x0

/* Slower full frequency range default timings for x32 operation*/
#define SDP_SDRC_SHARING		0x00000100
#define SDP_SDRC_MR_0_SDR		0x00000031

#ifdef CONFIG_3430ZEBU
#define SDP_SDRC_MDCFG_0_DDR	(0x02582019|B_ALL) /* Infin ddr module */
#else
#define SDP_SDRC_MDCFG_0_DDR	(0x02584019|B_ALL) /* Infin ddr module */
#endif

#define SDP_SDRC_MR_0_DDR		0x00000032

/* Diabling power down mode using CKE pin */
#define SDP_SDRC_POWER_POP      0x00000081

/* optimized timings good for current shipping parts */
#define SDP_3430_SDRC_RFR_CTRL_100MHz   0x0002da01
#define SDP_3430_SDRC_RFR_CTRL_133MHz   0x0003de01 /* 7.8us/7.5ns - 50=0x3de */
#define SDP_3430_SDRC_RFR_CTRL_165MHz   0x0004e201 /* 7.8us/6ns - 50=0x4e2 */

#define DLL_OFFSET              0
#define DLL_WRITEDDRCLKX2DIS    1
#define DLL_ENADLL              1
#define DLL_LOCKDLL             0
#define DLL_DLLPHASE_72         0
#define DLL_DLLPHASE_90         1

// rkw - need to find of 90/72 degree recommendation for speed like before.
#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \
    (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))

/* Infineon part of 3430SDP (133MHz optimized) ~ 7.5ns
 *	TDAL = Twr/Tck + Trp/tck = 15/7.5 + 22.5/7.5 = 2 + 3 = 5
 *	TDPL = 15/7.5	= 2
 *	TRRD = 15/2.5	= 2
 *	TRCD = 22.5/7.5	= 3
 *	TRP = 22.5/7.5	= 3
 *	TRAS = 45/7.5	= 6
 *	TRC = 65/7.5	= 8.6->9
 *	TRFC = 75/7.5	= 10
 *   ACTIMB
 *	TCKE = 2
 *	XSR = 120/7.5 = 16
 */
#define INFINEON_TDAL_133   5
#define INFINEON_TDPL_133   2
#define INFINEON_TRRD_133   2
#define INFINEON_TRCD_133   3
#define INFINEON_TRP_133    3
#define INFINEON_TRAS_133   6
#define INFINEON_TRC_133    9
#define INFINEON_TRFC_133  10
#define INFINEON_V_ACTIMA_133 ((INFINEON_TRFC_133 << 27) | (INFINEON_TRC_133 << 22) | (INFINEON_TRAS_133 << 18) \
		|(INFINEON_TRP_133 << 15) | (INFINEON_TRCD_133 << 12) |(INFINEON_TRRD_133 << 9) |(INFINEON_TDPL_133 << 6) \
		| (INFINEON_TDAL_133))

#define INFINEON_TWTR_133   1
#define INFINEON_TCKE_133   2
#define INFINEON_TXP_133    2
#define INFINEON_XSR_133   16
#define INFINEON_V_ACTIMB_133 ((INFINEON_TCKE_133 << 12) | (INFINEON_XSR_133 << 0)) | \
				(INFINEON_TXP_133 << 8) | (INFINEON_TWTR_133 << 16)

#define INFINEON_V_ACTIMA_100 INFINEON_V_ACTIMA_133
#define INFINEON_V_ACTIMB_100 INFINEON_V_ACTIMB_133


/* Infineon part of 3430SDP (165MHz optimized) 6.06ns
 *   ACTIMA
 *	TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
 *	TDPL (Twr) = 15/6	= 2.5 -> 3
 *	TRRD = 12/6	= 2
 *	TRCD = 18/6	= 3
 *	TRP = 18/6	= 3
 *	TRAS = 42/6	= 7
 *	TRC = 60/6	= 10
 *	TRFC = 72/6	= 12
 *   ACTIMB
 *	TCKE = 2
 *	XSR = 120/6 = 20
 */
#define INFINEON_TDAL_165   6
#define INFINEON_TDPL_165   3
#define INFINEON_TRRD_165   2
#define INFINEON_TRCD_165   3
#define INFINEON_TRP_165    3
#define INFINEON_TRAS_165   7
#define INFINEON_TRC_165   10
#define INFINEON_TRFC_165  12
#define INFINEON_V_ACTIMA_165 ((INFINEON_TRFC_165 << 27) | (INFINEON_TRC_165 << 22) | (INFINEON_TRAS_165 << 18) \
		| (INFINEON_TRP_165 << 15) | (INFINEON_TRCD_165 << 12) |(INFINEON_TRRD_165 << 9) | \
		(INFINEON_TDPL_165 << 6) | (INFINEON_TDAL_165))

#define INFINEON_TWTR_165   1
#define INFINEON_TCKE_165   2
#define INFINEON_TXP_165    2
#define INFINEON_XSR_165    20
#define INFINEON_V_ACTIMB_165 ((INFINEON_TCKE_165 << 12) | (INFINEON_XSR_165 << 0)) | \
				(INFINEON_TXP_165 << 8) | (INFINEON_TWTR_165 << 16)

/* Micron part of 3430 EVM (133MHz optimized) ~ 7.5ns
 *	TDAL = Twr/Tck + Trp/tck = 15/7.5 + 22.5/7.5 = 2 + 3 = 5
 *	TDPL =  15/7.5   = 2
 *	TRRD =  15/7.5   = 2
 *	TRCD =  22.5/7.5 = 3
 *	TRP  =  22.5/7.5 = 3
 *	TRAS =  45/7.5   = 6
 *	TRC  =  75/7.5   = 10
 *	TRFC =  125/7.5  = 16.6->17
 *   ACTIMB
 *	TWTR =  1
 *	TCKE =  1
 *	TXSR =  138/7.5  = 18.3->19
 *	TXP  =  25/7.5   = 3.3->4
 */
#define MICRON_TDAL_133   5
#define MICRON_TDPL_133   2
#define MICRON_TRRD_133   2
#define MICRON_TRCD_133   3
#define MICRON_TRP_133    3
#define MICRON_TRAS_133   6
#define MICRON_TRC_133    10
#define MICRON_TRFC_133   17
#define MICRON_V_ACTIMA_133 ((MICRON_TRFC_133 << 27) | (MICRON_TRC_133 << 22) | (MICRON_TRAS_133 << 18) \
		|(MICRON_TRP_133 << 15) | (MICRON_TRCD_133 << 12) |(MICRON_TRRD_133 << 9) |(MICRON_TDPL_133 << 6) \
		| (MICRON_TDAL_133))

#define MICRON_TWTR_133   1
#define MICRON_TCKE_133   1
#define MICRON_TXSR_133   19
#define MICRON_TXP_133    4
#define MICRON_V_ACTIMB_133 ((MICRON_TWTR_133 << 16) | (MICRON_TCKE_133 << 12) | (MICRON_TXP_133 << 8) \
		| (MICRON_TXSR_133 << 0))

#define MICRON_V_ACTIMA_100 MICRON_V_ACTIMA_133
#define MICRON_V_ACTIMB_100 MICRON_V_ACTIMB_133

/* Micron part of 3430 EVM (165MHz optimized) 6.06ns
 *   ACTIMA
 *	TDAL = Twr/Tck + Trp/tck = 15/6 + 18 /6 = 2.5 + 3 = 5.5 -> 6
 *	TDPL (Twr) = 15/6	= 2.5 -> 3
 *	TRRD = 12/6	= 2
 *	TRCD = 18/6 = 3
 *	TRP = 18/6	= 3
 *	TRAS = 42/6	= 7
 *	TRC = 60/6	= 10
 *	TRFC = 125/6	= 21
 *   ACTIMB
 *	TWTR =  1
 *	TCKE =  1
 *	TXSR =  138/6  = 23
 *	TXP  =  25/6   = 4.1 ~5
 */
#define MICRON_TDAL_165   6
#define MICRON_TDPL_165   3
#define MICRON_TRRD_165   2
#define MICRON_TRCD_165   3
#define MICRON_TRP_165    3
#define MICRON_TRAS_165   7
#define MICRON_TRC_165   10
#define MICRON_TRFC_165  21
#define MICRON_V_ACTIMA_165 ((MICRON_TRFC_165 << 27) | (MICRON_TRC_165 << 22) | (MICRON_TRAS_165 << 18) \
		| (MICRON_TRP_165 << 15) | (MICRON_TRCD_165 << 12) |(MICRON_TRRD_165 << 9) | \
		(MICRON_TDPL_165 << 6) | (MICRON_TDAL_165))

#define MICRON_TWTR_165   1
#define MICRON_TCKE_165   1
#define MICRON_TXP_165    5
#define MICRON_XSR_165    23
#define MICRON_V_ACTIMB_165 ((MICRON_TCKE_165 << 12) | (MICRON_XSR_165 << 0)) | \
				(MICRON_TXP_165 << 8) | (MICRON_TWTR_165 << 16)

/* New and compatability speed defines */
#if defined(PRCM_CLK_CFG2_200MHZ) || defined(PRCM_CONFIG_II) || defined(PRCM_CONFIG_5B)
# define L3_100MHZ   /* Use with <= 100MHz SDRAM */
#elif defined (PRCM_CLK_CFG2_266MHZ) || defined(PRCM_CONFIG_III) || defined(PRCM_CONFIG_5A)
# define L3_133MHZ    /* Use with <= 133MHz SDRAM*/
#elif  defined(PRCM_CLK_CFG2_332MHZ) || defined(PRCM_CONFIG_I) || defined(PRCM_CONFIG_2)
# define L3_165MHZ    /* Use with <= 165MHz SDRAM (L3=166 on 3430) */