divclkctrl.rpt

该程序是用VHDL语言实现的时钟分频程序

  _EQ022 = !_LC7_D12 &  _LC9_D12
         # !_LC2_D14 &  _LC9_D12
         #  _LC2_D14 &  _LC7_D12 & !_LC9_D12;

-- Node name is '|DIVCLK:71|:23' = '|DIVCLK:71|counter111' 
-- Equation name is '_LC2_D12', type is buried 
_LC2_D12 = DFF( _EQ023,  SYSCLK,  VCC,  VCC);
  _EQ023 =  _LC2_D12 & !_LC9_D12
         #  _LC2_D12 & !_LC7_D12
         #  _LC2_D12 & !_LC2_D14
         # !_LC2_D12 &  _LC2_D14 &  _LC7_D12 &  _LC9_D12;

-- Node name is '|DIVCLK:71|:22' = '|DIVCLK:71|counter112' 
-- Equation name is '_LC6_D12', type is buried 
_LC6_D12 = DFF( _EQ024,  SYSCLK,  VCC,  VCC);
  _EQ024 = !_LC4_D12 &  _LC6_D12 & !_LC8_D12
         # !_LC2_D12 &  _LC6_D12 & !_LC8_D12
         #  _LC2_D12 &  _LC4_D12 & !_LC6_D12 & !_LC8_D12;

-- Node name is '|DIVCLK:71|LPM_ADD_SUB:88|addcore:adder|:99' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_D22', type is buried 
_LC7_D22 = LCELL( _EQ025);
  _EQ025 =  _LC1_D22 &  _LC2_D22 &  _LC8_D22;

-- Node name is '|DIVCLK:71|LPM_ADD_SUB:88|addcore:adder|:111' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_D14', type is buried 
_LC6_D14 = LCELL( _EQ026);
  _EQ026 =  _LC6_D16 &  _LC7_D22 &  _LC9_D14 &  _LC10_D14;

-- Node name is '|DIVCLK:71|LPM_ADD_SUB:88|addcore:adder|:115' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_D14', type is buried 
_LC1_D14 = LCELL( _EQ027);
  _EQ027 =  _LC5_D14 &  _LC6_D14;

-- Node name is '|DIVCLK:71|LPM_ADD_SUB:88|addcore:adder|:123' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_D14', type is buried 
_LC2_D14 = LCELL( _EQ028);
  _EQ028 =  _LC5_D14 &  _LC6_D14 &  _LC7_D14 &  _LC8_D14;

-- Node name is '|DIVCLK:71|LPM_ADD_SUB:88|addcore:adder|:131' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_D12', type is buried 
_LC4_D12 = LCELL( _EQ029);
  _EQ029 =  _LC2_D14 &  _LC7_D12 &  _LC9_D12;

-- Node name is '|DIVCLK:71|LPM_ADD_SUB:146|addcore:adder|:67' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_C13', type is buried 
_LC3_C13 = LCELL( _EQ030);
  _EQ030 =  _LC2_C13 &  _LC8_C13;

-- Node name is '|DIVCLK:71|LPM_ADD_SUB:146|addcore:adder|:71' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_C13', type is buried 
_LC1_C13 = LCELL( _EQ031);
  _EQ031 =  _LC2_C13 &  _LC7_C13 &  _LC8_C13;

-- Node name is '|DIVCLK:71|LPM_ADD_SUB:146|addcore:adder|:75' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_C15', type is buried 
_LC3_C15 = LCELL( _EQ032);
  _EQ032 =  _LC1_C13 &  _LC6_C15;

-- Node name is '|DIVCLK:71|LPM_ADD_SUB:146|addcore:adder|:79' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_C15', type is buried 
_LC7_C15 = LCELL( _EQ033);
  _EQ033 =  _LC2_C15 &  _LC3_C15;

-- Node name is '|DIVCLK:71|:7' = '|DIVCLK:71|temp3' 
-- Equation name is '_LC6_C22', type is buried 
_LC6_C22 = DFF( _EQ034,  SYSCLK,  VCC,  VCC);
  _EQ034 = !_LC6_C13 &  _LC6_C22
         #  _LC6_C22 & !_LC8_D12
         # !_LC1_C17 &  _LC6_C22
         #  _LC1_C17 &  _LC6_C13 & !_LC6_C22 &  _LC8_D12;

-- Node name is '|DIVCLK:71|:6' = '|DIVCLK:71|temp4' 
-- Equation name is '_LC6_D22', type is buried 
_LC6_D22 = DFF( _EQ035,  SYSCLK,  VCC,  VCC);
  _EQ035 = !_LC2_C22 &  _LC6_D22
         #  _LC6_D22 &  _LC7_C22
         #  _LC2_C22 & !_LC6_D22 & !_LC7_C22;

-- Node name is '|DIVCLK:71|~102~1' 
-- Equation name is '_LC4_D14', type is buried 
-- synthesized logic cell 
_LC4_D14 = LCELL( _EQ036);
  _EQ036 =  _LC5_D14
         # !_LC7_D14
         # !_LC8_D14;

-- Node name is '|DIVCLK:71|~102~2' 
-- Equation name is '_LC3_D14', type is buried 
-- synthesized logic cell 
_LC3_D14 = LCELL( _EQ037);
  _EQ037 =  _LC10_D14
         #  _LC6_D16
         #  _LC9_D14
         #  _LC4_D14;

-- Node name is '|DIVCLK:71|~102~3' 
-- Equation name is '_LC3_D12', type is buried 
-- synthesized logic cell 
_LC3_D12 = LCELL( _EQ038);
  _EQ038 =  _LC9_D12
         # !_LC6_D12
         #  _LC2_D12;

-- Node name is '|DIVCLK:71|~102~4' 
-- Equation name is '_LC8_C22', type is buried 
-- synthesized logic cell 
_LC8_C22 = LCELL( _EQ039);
  _EQ039 =  _LC6_C13 &  _LC8_D12 &  _LC9_C22;

-- Node name is '|DIVCLK:71|:102' 
-- Equation name is '_LC8_D12', type is buried 
!_LC8_D12 = _LC8_D12~NOT;
_LC8_D12~NOT = LCELL( _EQ040);
  _EQ040 =  _LC3_D14
         # !_LC7_D12
         #  _LC3_D12
         # !_LC7_D22;

-- Node name is '|DIVCLK:71|~153~1' 
-- Equation name is '_LC1_C15', type is buried 
-- synthesized logic cell 
_LC1_C15 = LCELL( _EQ041);
  _EQ041 =  _LC6_C15
         # !_LC8_C15
         # !_LC2_C15;

-- Node name is '|DIVCLK:71|:153' 
-- Equation name is '_LC6_C13', type is buried 
!_LC6_C13 = _LC6_C13~NOT;
_LC6_C13~NOT = LCELL( _EQ042);
  _EQ042 =  _LC2_C13
         # !_LC8_C13
         #  _LC7_C13
         #  _LC1_C15;

-- Node name is '|DIVCLK:71|:180' 
-- Equation name is '_LC1_C17', type is buried 
_LC1_C17 = LCELL( _EQ043);
  _EQ043 = !_LC3_C17 & !_LC7_C17 &  _LC8_C17;

-- Node name is '|DIVCLK:71|:201' 
-- Equation name is '_LC2_C22', type is buried 
!_LC2_C22 = _LC2_C22~NOT;
_LC2_C22~NOT = LCELL( _EQ044);
  _EQ044 =  _LC5_C22
         # !_LC4_C22
         # !_LC1_C22;

-- Node name is '|DIVCLK:71|~268~1' 
-- Equation name is '_LC9_C22', type is buried 
-- synthesized logic cell 
_LC9_C22 = LCELL( _EQ045);
  _EQ045 =  _LC1_C17 & !_LC2_C22;

-- Node name is '|DIVCLK:71|:351' 
-- Equation name is '_LC6_C17', type is buried 
_LC6_C17 = LCELL( _EQ046);
  _EQ046 = !_LC6_C13 &  _LC8_C17
         # !_LC3_C17 &  _LC7_C17 &  _LC8_C17
         #  _LC3_C17 &  _LC6_C13 &  _LC7_C17 & !_LC8_C17
         #  _LC3_C17 & !_LC7_C17 &  _LC8_C17;

-- Node name is '|DIVCLK:71|:357' 
-- Equation name is '_LC2_C17', type is buried 
_LC2_C17 = LCELL( _EQ047);
  _EQ047 =  _LC3_C17 & !_LC6_C13
         # !_LC3_C17 &  _LC6_C13 &  _LC7_C17
         #  _LC3_C17 & !_LC7_C17;

-- Node name is '|DIVCLK:71|~442~1' 
-- Equation name is '_LC3_C22', type is buried 
-- synthesized logic cell 
_LC3_C22 = LCELL( _EQ048);
  _EQ048 = !_LC4_C22 &  _LC9_C22
         # !_LC1_C22 &  _LC9_C22
         #  _LC7_C22;

-- Node name is '|DIVCLK:71|~448~1' 
-- Equation name is '_LC10_C22', type is buried 
-- synthesized logic cell 
_LC10_C22 = LCELL( _EQ049);
  _EQ049 = !_LC1_C22 &  _LC9_C22
         #  _LC7_C22;

-- Node name is '|DIVCLK:71|~454~1' 
-- Equation name is '_LC7_C22', type is buried 
-- synthesized logic cell 
!_LC7_C22 = _LC7_C22~NOT;
_LC7_C22~NOT = LCELL( _EQ050);
  _EQ050 =  _LC1_C17 &  _LC6_C13 &  _LC8_D12;



Project Information                        e:\chicago2.0\divclk\divclkctrl.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX6000' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 12,900K