📄 divclkctrl.rpt
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** BURIED LOGIC **
Fan-In Fan-Out
IOC LC Row Col Primitive Code INP FBK OUT FBK Name
- 7 D 22 AND2 0 3 0 5 |DIVCLK:71|LPM_ADD_SUB:88|addcore:adder|:99
- 6 D 14 AND2 0 4 0 4 |DIVCLK:71|LPM_ADD_SUB:88|addcore:adder|:111
- 1 D 14 AND2 0 2 0 1 |DIVCLK:71|LPM_ADD_SUB:88|addcore:adder|:115
- 2 D 14 AND2 0 4 0 4 |DIVCLK:71|LPM_ADD_SUB:88|addcore:adder|:123
- 4 D 12 AND2 0 3 0 1 |DIVCLK:71|LPM_ADD_SUB:88|addcore:adder|:131
- 3 C 13 AND2 0 2 0 1 |DIVCLK:71|LPM_ADD_SUB:146|addcore:adder|:67
- 1 C 13 AND2 0 3 0 2 |DIVCLK:71|LPM_ADD_SUB:146|addcore:adder|:71
- 3 C 15 AND2 0 2 0 2 |DIVCLK:71|LPM_ADD_SUB:146|addcore:adder|:75
- 7 C 15 AND2 0 2 0 1 |DIVCLK:71|LPM_ADD_SUB:146|addcore:adder|:79
- 6 D 22 DFF 1 3 1 1 |DIVCLK:71|temp4 (|DIVCLK:71|:6)
- 6 C 22 DFF 1 4 1 1 |DIVCLK:71|temp3 (|DIVCLK:71|:7)
- 5 C 22 DFF 1 4 0 2 |DIVCLK:71|counter42 (|DIVCLK:71|:10)
- 4 C 22 DFF 1 4 0 3 |DIVCLK:71|counter41 (|DIVCLK:71|:11)
- 1 C 22 DFF 1 2 0 5 |DIVCLK:71|counter40 (|DIVCLK:71|:12)
- 8 C 17 DFF 1 3 0 3 |DIVCLK:71|counter32 (|DIVCLK:71|:13)
- 3 C 17 DFF 1 3 0 4 |DIVCLK:71|counter31 (|DIVCLK:71|:14)
- 7 C 17 DFF 1 4 0 4 |DIVCLK:71|counter30 (|DIVCLK:71|:15)
- 8 C 15 DFF 1 4 0 2 |DIVCLK:71|counter25 (|DIVCLK:71|:16)
- 2 C 15 DFF 1 4 0 3 |DIVCLK:71|counter24 (|DIVCLK:71|:17)
- 6 C 15 DFF 1 4 0 3 |DIVCLK:71|counter23 (|DIVCLK:71|:18)
- 7 C 13 DFF 1 4 0 3 |DIVCLK:71|counter22 (|DIVCLK:71|:19)
- 2 C 13 DFF 1 4 0 4 |DIVCLK:71|counter21 (|DIVCLK:71|:20)
- 8 C 13 DFF 1 2 0 5 |DIVCLK:71|counter20 (|DIVCLK:71|:21)
- 6 D 12 DFF 1 4 0 2 |DIVCLK:71|counter112 (|DIVCLK:71|:22)
- 2 D 12 DFF 1 4 0 3 |DIVCLK:71|counter111 (|DIVCLK:71|:23)
- 9 D 12 DFF 1 3 0 4 |DIVCLK:71|counter110 (|DIVCLK:71|:24)
- 7 D 12 DFF 1 3 0 5 |DIVCLK:71|counter19 (|DIVCLK:71|:25)
- 7 D 14 DFF 1 4 0 3 |DIVCLK:71|counter18 (|DIVCLK:71|:26)
- 8 D 14 DFF 1 4 0 4 |DIVCLK:71|counter17 (|DIVCLK:71|:27)
- 5 D 14 DFF 1 2 0 5 |DIVCLK:71|counter16 (|DIVCLK:71|:28)
- 9 D 14 DFF 1 4 0 3 |DIVCLK:71|counter15 (|DIVCLK:71|:29)
- 10 D 14 DFF 1 3 0 4 |DIVCLK:71|counter14 (|DIVCLK:71|:30)
- 6 D 16 DFF 1 3 0 5 |DIVCLK:71|counter13 (|DIVCLK:71|:31)
- 2 D 22 DFF 1 4 0 2 |DIVCLK:71|counter12 (|DIVCLK:71|:32)
- 8 D 22 DFF 1 3 0 3 |DIVCLK:71|counter11 (|DIVCLK:71|:33)
- 1 D 22 DFF 1 1 0 4 |DIVCLK:71|counter10 (|DIVCLK:71|:34)
- 4 D 14 OR2 s 0 3 0 1 |DIVCLK:71|~102~1
- 3 D 14 OR2 s 0 4 0 1 |DIVCLK:71|~102~2
- 3 D 12 OR2 s 0 3 0 1 |DIVCLK:71|~102~3
- 8 C 22 AND2 s 0 3 0 2 |DIVCLK:71|~102~4
- 8 D 12 OR2 ! 0 4 0 19 |DIVCLK:71|:102
- 1 C 15 OR2 s 0 3 0 1 |DIVCLK:71|~153~1
- 6 C 13 OR2 ! 0 4 0 11 |DIVCLK:71|:153
- 1 C 17 AND2 0 3 0 4 |DIVCLK:71|:180
- 2 C 22 OR2 ! 0 3 0 3 |DIVCLK:71|:201
- 9 C 22 AND2 s 0 2 0 3 |DIVCLK:71|~268~1
- 6 C 17 OR2 0 4 0 1 |DIVCLK:71|:351
- 2 C 17 OR2 0 3 0 1 |DIVCLK:71|:357
- 3 C 22 OR2 s 0 4 0 1 |DIVCLK:71|~442~1
- 10 C 22 OR2 s 0 3 0 1 |DIVCLK:71|~448~1
- 7 C 22 AND2 s ! 0 3 0 4 |DIVCLK:71|~454~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
$ = Driven by fast output logic cell
p = Packed register
Device-Specific Information: e:\chicago2.0\divclk\divclkctrl.rpt
divclkctrl
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 7/ 48( 14%) 0/20( 0%) 1/20( 5%) 0/20( 0%)
D: 5/ 96( 5%) 0/ 48( 0%) 5/ 48( 10%) 1/20( 5%) 1/20( 5%) 0/20( 0%)
E: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
F: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/20( 5%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/20( 5%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/20( 5%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\chicago2.0\divclk\divclkctrl.rpt
divclkctrl
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 27 SYSCLK
Device-Specific Information: e:\chicago2.0\divclk\divclkctrl.rpt
divclkctrl
** EQUATIONS **
SYSCLK : INPUT;
-- Node name is 'LED1'
-- Equation name is 'LED1', type is output
LED1 = _LC6_D22;
-- Node name is 'LED2'
-- Equation name is 'LED2', type is output
LED2 = _LC6_C22;
-- Node name is '|DIVCLK:71|:34' = '|DIVCLK:71|counter10'
-- Equation name is '_LC1_D22', type is buried
_LC1_D22 = DFF(!_LC1_D22, SYSCLK, VCC, VCC);
-- Node name is '|DIVCLK:71|:33' = '|DIVCLK:71|counter11'
-- Equation name is '_LC8_D22', type is buried
_LC8_D22 = DFF( _EQ001, SYSCLK, VCC, VCC);
_EQ001 = !_LC1_D22 & !_LC8_D12 & _LC8_D22
# _LC1_D22 & !_LC8_D12 & !_LC8_D22;
-- Node name is '|DIVCLK:71|:32' = '|DIVCLK:71|counter12'
-- Equation name is '_LC2_D22', type is buried
_LC2_D22 = DFF( _EQ002, SYSCLK, VCC, VCC);
_EQ002 = _LC2_D22 & !_LC8_D12 & !_LC8_D22
# !_LC1_D22 & _LC2_D22 & !_LC8_D12
# _LC1_D22 & !_LC2_D22 & !_LC8_D12 & _LC8_D22;
-- Node name is '|DIVCLK:71|:31' = '|DIVCLK:71|counter13'
-- Equation name is '_LC6_D16', type is buried
_LC6_D16 = DFF( _EQ003, SYSCLK, VCC, VCC);
_EQ003 = _LC6_D16 & !_LC7_D22 & !_LC8_D12
# !_LC6_D16 & _LC7_D22 & !_LC8_D12;
-- Node name is '|DIVCLK:71|:30' = '|DIVCLK:71|counter14'
-- Equation name is '_LC10_D14', type is buried
_LC10_D14 = DFF( _EQ004, SYSCLK, VCC, VCC);
_EQ004 = !_LC6_D16 & _LC10_D14
# !_LC7_D22 & _LC10_D14
# _LC6_D16 & _LC7_D22 & !_LC10_D14;
-- Node name is '|DIVCLK:71|:29' = '|DIVCLK:71|counter15'
-- Equation name is '_LC9_D14', type is buried
_LC9_D14 = DFF( _EQ005, SYSCLK, VCC, VCC);
_EQ005 = _LC9_D14 & !_LC10_D14
# !_LC6_D16 & _LC9_D14
# !_LC7_D22 & _LC9_D14
# _LC6_D16 & _LC7_D22 & !_LC9_D14 & _LC10_D14;
-- Node name is '|DIVCLK:71|:28' = '|DIVCLK:71|counter16'
-- Equation name is '_LC5_D14', type is buried
_LC5_D14 = DFF( _EQ006, SYSCLK, VCC, VCC);
_EQ006 = _LC5_D14 & !_LC6_D14
# !_LC5_D14 & _LC6_D14;
-- Node name is '|DIVCLK:71|:27' = '|DIVCLK:71|counter17'
-- Equation name is '_LC8_D14', type is buried
_LC8_D14 = DFF( _EQ007, SYSCLK, VCC, VCC);
_EQ007 = !_LC5_D14 & !_LC8_D12 & _LC8_D14
# !_LC6_D14 & !_LC8_D12 & _LC8_D14
# _LC5_D14 & _LC6_D14 & !_LC8_D12 & !_LC8_D14;
-- Node name is '|DIVCLK:71|:26' = '|DIVCLK:71|counter18'
-- Equation name is '_LC7_D14', type is buried
_LC7_D14 = DFF( _EQ008, SYSCLK, VCC, VCC);
_EQ008 = !_LC1_D14 & _LC7_D14 & !_LC8_D12
# _LC7_D14 & !_LC8_D12 & !_LC8_D14
# _LC1_D14 & !_LC7_D14 & !_LC8_D12 & _LC8_D14;
-- Node name is '|DIVCLK:71|:25' = '|DIVCLK:71|counter19'
-- Equation name is '_LC7_D12', type is buried
_LC7_D12 = DFF( _EQ009, SYSCLK, VCC, VCC);
_EQ009 = !_LC2_D14 & _LC7_D12 & !_LC8_D12
# _LC2_D14 & !_LC7_D12 & !_LC8_D12;
-- Node name is '|DIVCLK:71|:21' = '|DIVCLK:71|counter20'
-- Equation name is '_LC8_C13', type is buried
_LC8_C13 = DFF( _EQ010, SYSCLK, VCC, VCC);
_EQ010 = _LC8_C13 & !_LC8_D12
# !_LC8_C13 & _LC8_D12;
-- Node name is '|DIVCLK:71|:20' = '|DIVCLK:71|counter21'
-- Equation name is '_LC2_C13', type is buried
_LC2_C13 = DFF( _EQ011, SYSCLK, VCC, VCC);
_EQ011 = _LC2_C13 & !_LC8_D12
# _LC2_C13 & !_LC6_C13 & !_LC8_C13
# !_LC2_C13 & !_LC6_C13 & _LC8_C13 & _LC8_D12;
-- Node name is '|DIVCLK:71|:19' = '|DIVCLK:71|counter22'
-- Equation name is '_LC7_C13', type is buried
_LC7_C13 = DFF( _EQ012, SYSCLK, VCC, VCC);
_EQ012 = _LC7_C13 & !_LC8_D12
# !_LC3_C13 & !_LC6_C13 & _LC7_C13
# _LC3_C13 & !_LC6_C13 & !_LC7_C13 & _LC8_D12;
-- Node name is '|DIVCLK:71|:18' = '|DIVCLK:71|counter23'
-- Equation name is '_LC6_C15', type is buried
_LC6_C15 = DFF( _EQ013, SYSCLK, VCC, VCC);
_EQ013 = _LC6_C15 & !_LC8_D12
# !_LC1_C13 & !_LC6_C13 & _LC6_C15
# _LC1_C13 & !_LC6_C13 & !_LC6_C15 & _LC8_D12;
-- Node name is '|DIVCLK:71|:17' = '|DIVCLK:71|counter24'
-- Equation name is '_LC2_C15', type is buried
_LC2_C15 = DFF( _EQ014, SYSCLK, VCC, VCC);
_EQ014 = _LC2_C15 & !_LC8_D12
# _LC2_C15 & !_LC3_C15 & !_LC6_C13
# !_LC2_C15 & _LC3_C15 & !_LC6_C13 & _LC8_D12;
-- Node name is '|DIVCLK:71|:16' = '|DIVCLK:71|counter25'
-- Equation name is '_LC8_C15', type is buried
_LC8_C15 = DFF( _EQ015, SYSCLK, VCC, VCC);
_EQ015 = _LC8_C15 & !_LC8_D12
# !_LC6_C13 & !_LC7_C15 & _LC8_C15
# !_LC6_C13 & _LC7_C15 & !_LC8_C15 & _LC8_D12;
-- Node name is '|DIVCLK:71|:15' = '|DIVCLK:71|counter30'
-- Equation name is '_LC7_C17', type is buried
_LC7_C17 = DFF( _EQ016, SYSCLK, VCC, VCC);
_EQ016 = !_LC1_C17 & _LC6_C13 & !_LC7_C17 & _LC8_D12
# !_LC6_C13 & _LC7_C17
# _LC7_C17 & !_LC8_D12;
-- Node name is '|DIVCLK:71|:14' = '|DIVCLK:71|counter31'
-- Equation name is '_LC3_C17', type is buried
_LC3_C17 = DFF( _EQ017, SYSCLK, VCC, VCC);
_EQ017 = _LC3_C17 & !_LC8_D12
# _LC2_C17 & _LC8_D12;
-- Node name is '|DIVCLK:71|:13' = '|DIVCLK:71|counter32'
-- Equation name is '_LC8_C17', type is buried
_LC8_C17 = DFF( _EQ018, SYSCLK, VCC, VCC);
_EQ018 = _LC8_C17 & !_LC8_D12
# _LC6_C17 & _LC8_D12;
-- Node name is '|DIVCLK:71|:12' = '|DIVCLK:71|counter40'
-- Equation name is '_LC1_C22', type is buried
_LC1_C22 = DFF( _EQ019, SYSCLK, VCC, VCC);
_EQ019 = _LC1_C22 & _LC7_C22
# !_LC1_C22 & !_LC7_C22;
-- Node name is '|DIVCLK:71|:11' = '|DIVCLK:71|counter41'
-- Equation name is '_LC4_C22', type is buried
_LC4_C22 = DFF( _EQ020, SYSCLK, VCC, VCC);
_EQ020 = _LC1_C22 & !_LC4_C22 & _LC8_C22
# _LC4_C22 & _LC10_C22;
-- Node name is '|DIVCLK:71|:10' = '|DIVCLK:71|counter42'
-- Equation name is '_LC5_C22', type is buried
_LC5_C22 = DFF( _EQ021, SYSCLK, VCC, VCC);
_EQ021 = _LC2_C22 & _LC8_C22
# _LC3_C22 & _LC5_C22;
-- Node name is '|DIVCLK:71|:24' = '|DIVCLK:71|counter110'
-- Equation name is '_LC9_D12', type is buried
_LC9_D12 = DFF( _EQ022, SYSCLK, VCC, VCC);
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