📄 2410lib.txt
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0008d0 e1a00004 MOV r0,r4
0008d4 ebfffffe BL strlen
0008d8 e2408001 SUB r8,r0,#1
;;;361
;;;362 if(lastIndex<0)
0008dc e3580000 CMP r8,#0
0008e0 aa000003 BGE |L1.2292|
;;;363 return -1;
0008e4 e3e00000 MVN r0,#0
|L1.2280|
0008e8 e28dd024 ADD sp,sp,#0x24
0008ec e8bd43f0 POP {r4-r9,lr}
;;;364
;;;365 if(pString[lastIndex]=='h' || pString[lastIndex]=='H' )
;;;366 {
;;;367 base = 16;
;;;368 pString[lastIndex] = 0;
;;;369 lastIndex--;
;;;370 }
;;;371
;;;372 if(base==10)
;;;373 {
;;;374 nResult = atoi(pString);
;;;375 nResult = minus ? (-1*nResult):nResult;
;;;376 }
;;;377 else
;;;378 {
;;;379 for(i=0;i<=lastIndex;i++)
;;;380 {
;;;381 if(isalpha(pString[i]))
;;;382 {
;;;383 if(isupper(pString[i]))
;;;384 nResult = (nResult<<4) + pString[i] - 'A' + 10;
;;;385 else
;;;386 nResult = (nResult<<4) + pString[i] - 'a' + 10;
;;;387 }
;;;388 else
;;;389 nResult = (nResult<<4) + pString[i] - '0';
;;;390 }
;;;391 nResult = minus ? (-1*nResult):nResult;
;;;392 }
;;;393 return nResult;
;;;394 }
0008f0 e12fff1e BX lr
|L1.2292|
0008f4 e7d40008 LDRB r0,[r4,r8] ;365
0008f8 e3500068 CMP r0,#0x68 ;365
0008fc 0a000002 BEQ |L1.2316|
000900 e7d40008 LDRB r0,[r4,r8] ;365
000904 e3500048 CMP r0,#0x48 ;365
000908 1a000003 BNE |L1.2332|
|L1.2316|
00090c e3a05010 MOV r5,#0x10 ;367
000910 e3a00000 MOV r0,#0 ;368
000914 e7c40008 STRB r0,[r4,r8] ;368
000918 e2488001 SUB r8,r8,#1 ;369
|L1.2332|
00091c e355000a CMP r5,#0xa ;372
000920 1a000009 BNE |L1.2380|
000924 e1a00004 MOV r0,r4 ;374
000928 ebfffffe BL atoi
00092c e1a07000 MOV r7,r0 ;374
000930 e3560000 CMP r6,#0 ;375
000934 0a000001 BEQ |L1.2368|
000938 e2670000 RSB r0,r7,#0 ;375
00093c ea000000 B |L1.2372|
|L1.2368|
000940 e1a00007 MOV r0,r7 ;375
|L1.2372|
000944 e1a07000 MOV r7,r0 ;375
000948 ea000021 B |L1.2516|
|L1.2380|
00094c e3a09000 MOV r9,#0 ;379
000950 ea000017 B |L1.2484|
|L1.2388|
000954 ebfffffe BL __rt_ctype_table
000958 e5900000 LDR r0,[r0,#0] ;381
00095c e7d41009 LDRB r1,[r4,r9] ;381
000960 e7d00001 LDRB r0,[r0,r1] ;381
000964 e3100098 TST r0,#0x98 ;381
000968 0a00000d BEQ |L1.2468|
00096c ebfffffe BL __rt_ctype_table
000970 e5900000 LDR r0,[r0,#0] ;383
000974 e7d41009 LDRB r1,[r4,r9] ;383
000978 e7d00001 LDRB r0,[r0,r1] ;383
00097c e3100010 TST r0,#0x10 ;383
000980 0a000003 BEQ |L1.2452|
000984 e7d40009 LDRB r0,[r4,r9] ;384
000988 e0800207 ADD r0,r0,r7,LSL #4 ;384
00098c e2407037 SUB r7,r0,#0x37 ;384
000990 ea000006 B |L1.2480|
|L1.2452|
000994 e7d40009 LDRB r0,[r4,r9] ;386
000998 e0800207 ADD r0,r0,r7,LSL #4 ;386
00099c e2407057 SUB r7,r0,#0x57 ;386
0009a0 ea000002 B |L1.2480|
|L1.2468|
0009a4 e7d40009 LDRB r0,[r4,r9] ;389
0009a8 e0800207 ADD r0,r0,r7,LSL #4 ;389
0009ac e2407030 SUB r7,r0,#0x30 ;389
|L1.2480|
0009b0 e2899001 ADD r9,r9,#1 ;379
|L1.2484|
0009b4 e1590008 CMP r9,r8 ;379
0009b8 daffffe5 BLE |L1.2388|
0009bc e3560000 CMP r6,#0 ;391
0009c0 0a000001 BEQ |L1.2508|
0009c4 e2670000 RSB r0,r7,#0 ;391
0009c8 ea000000 B |L1.2512|
|L1.2508|
0009cc e1a00007 MOV r0,r7 ;391
|L1.2512|
0009d0 e1a07000 MOV r7,r0 ;391
|L1.2516|
0009d4 e1a00007 MOV r0,r7 ;393
0009d8 eaffffc2 B |L1.2280|
;;;395
ENDP
timer_start PROC
;;;486 {
;;;487 rWTCON = ((PCLK/1000000-1)<<8)|(divider<<3); //Watch-dog timer control register
0009dc e3a01c31 MOV r1,#0x3100
0009e0 e1811180 ORR r1,r1,r0,LSL #3
0009e4 e3a02453 MOV r2,#0x53000000
0009e8 e5821000 STR r1,[r2,#0]
;;;488 rWTDAT = 0xffff; //Watch-dog timer data register
0009ec e51f1638 LDR r1,|L1.956|
0009f0 e5821004 STR r1,[r2,#4]
;;;489 rWTCNT = 0xffff; //Watch-dog count register
0009f4 e5821008 STR r1,[r2,#8]
;;;490
;;;491 rWTCON = rWTCON | (1<<5) | ~(1<<2); //May 06, 2002 SOP
0009f8 e3a01453 MOV r1,#0x53000000
0009fc e5911000 LDR r1,[r1,#0]
000a00 e3811020 ORR r1,r1,#0x20
000a04 e3e02004 MVN r2,#4
000a08 e1811002 ORR r1,r1,r2
000a0c e3a02453 MOV r2,#0x53000000
000a10 e5821000 STR r1,[r2,#0]
;;;492 }
000a14 e12fff1e BX lr
|L1.2584|
000a18 00000000 DCD f_nWhichUart
|L1.2588|
000a1c 08200800 DCB "\b\40\b\0"
ENDP
timer_stop PROC
;;;503 {
;;;504 rWTCON = ((PCLK/1000000-1)<<8);
000a20 e3a00c31 MOV r0,#0x3100
000a24 e3a01453 MOV r1,#0x53000000
000a28 e5810000 STR r0,[r1,#0]
;;;505 return (0xffff - rWTCNT);
000a2c e3a00453 MOV r0,#0x53000000
000a30 e5900008 LDR r0,[r0,#8]
000a34 e51f1680 LDR r1,|L1.956|
000a38 e0410000 SUB r0,r1,r0
;;;506 }
000a3c e12fff1e BX lr
;;;507
ENDP
change_value_MPLL PROC
;;;517 {
;;;518 rMPLLCON = (nMdiv<<12) | (nPdiv<<4) | nSdiv;
000a40 e1a03600 LSL r3,r0,#12
000a44 e1833201 ORR r3,r3,r1,LSL #4
000a48 e1833002 ORR r3,r3,r2
000a4c e3a0c313 MOV r12,#0x4c000000
000a50 e58c3004 STR r3,[r12,#4]
;;;519 }
000a54 e12fff1e BX lr
;;;520
ENDP
change_clock_divider PROC
;;;535 // 1,1 1:2:4
;;;536 rCLKDIVN = (nHdiv<<1) | nPdiv;
000a58 e1812080 ORR r2,r1,r0,LSL #1
000a5c e3a03313 MOV r3,#0x4c000000
000a60 e5832014 STR r2,[r3,#0x14]
;;;537
;;;538 }
000a64 e12fff1e BX lr
;;;539
ENDP
ChangeUPllValue PROC
;;;549 {
;;;550 rUPLLCON = (nMdiv<<12) | (nPdiv<<4) | nSdiv;
000a68 e1a03600 LSL r3,r0,#12
000a6c e1833201 ORR r3,r3,r1,LSL #4
000a70 e1833002 ORR r3,r3,r2
000a74 e3a0c313 MOV r12,#0x4c000000
000a78 e58c3008 STR r3,[r12,#8]
;;;551 }
000a7c e12fff1e BX lr
;;;552
ENDP
EnableMMU PROC
;;;600
;;;601 ctl = ARM_ReadControl();
000a80 e1a00000 MOV r0,r0
000a84 ee110f10 MRC p15,#0x0,r0,c1,c0,#0
000a88 e1a00000 MOV r0,r0
000a8c e1a01000 MOV r1,r0
;;;602 ctl |= (1 << 0);
000a90 e3811001 ORR r1,r1,#1
;;;603 ARM_WriteControl(ctl);
000a94 e1a00000 MOV r0,r0
000a98 ee011f10 MCR p15,#0x0,r1,c1,c0,#0
000a9c e1a00000 MOV r0,r0
;;;604 }
000aa0 e12fff1e BX lr
;;;605
ENDP
InitMMU PROC
;;;614 void InitMMU(unsigned int *pTranslationTable)
;;;615 {
000aa4 e92d4010 PUSH {r4,lr}
000aa8 e1a03000 MOV r3,r0
000aac e1a00723 LSR r0,r3,#14
000ab0 e1a00700 LSL r0,r0,#14
000ab4 ee020f10 MCR p15,#0x0,r0,c2,c0,#0
000ab8 e1a00000 MOV r0,r0
;;;616 int i;
;;;617 // Program the TTB
;;;618 ARM_WriteTTB((unsigned int) pTranslationTable);
;;;619 // Program the domain access register
;;;620 ARM_WriteDomain(0xC0000000); // domain 15: access are not checked
000abc e1a00000 MOV r0,r0
000ac0 e3a00103 MOV r0,#0xc0000000
000ac4 ee030f10 MCR p15,#0x0,r0,c3,c0,#0
000ac8 e1a00000 MOV r0,r0
;;;621
;;;622 // Reset table entries
;;;623 for (i = 0; i < 0x200; ++i)
000acc e3a04000 MOV r4,#0
000ad0 ea000002 B |L1.2784|
|L1.2772|
;;;624 pTranslationTable[i] = 0;
000ad4 e3a00000 MOV r0,#0
000ad8 e7830104 STR r0,[r3,r4,LSL #2]
000adc e2844001 ADD r4,r4,#1 ;623
|L1.2784|
000ae0 e3540c02 CMP r4,#0x200 ;623
000ae4 bafffffa BLT |L1.2772|
;;;625
;;;626 // Program level 1 page table entry
;;;627 pTranslationTable[0x0] =
000ae8 e59f0054 LDR r0,|L1.2884|
000aec e5830000 STR r0,[r3,#0]
;;;628 (0x300 << 20) | // Physical Address
;;;629 (1 << 10) | // Access in supervisor mode
;;;630 (15 << 5) | // Domain
;;;631 1 << 4 |
;;;632 0x2; // Set as 1 Mbyte section
;;;633 pTranslationTable[0x1] =
000af0 e2800601 ADD r0,r0,#0x100000
000af4 e5830004 STR r0,[r3,#4]
;;;634 (0x301 << 20) | // Physical Address
;;;635 (1 << 10) | // Access in supervisor mode
;;;636 (15 << 5) | // Domain
;;;637 1 << 4 |
;;;638 0x2; // Set as 1 Mbyte section
;;;639 pTranslationTable[0x2] =
000af8 e2800601 ADD r0,r0,#0x100000
000afc e5830008 STR r0,[r3,#8]
;;;640 (0x302 << 20) | // Physical Address
;;;641 (1 << 10) | // Access in supervisor mode
;;;642 (15 << 5) | // Domain
;;;643 1 << 4 |
;;;644 0x2; // Set as 1 Mbyte section
;;;645 pTranslationTable[0x3] =
000b00 e2800601 ADD r0,r0,#0x100000
000b04 e583000c STR r0,[r3,#0xc]
;;;646 (0x303 << 20) | // Physical Address
;;;647 (1 << 10) | // Access in supervisor mode
;;;648 (15 << 5) | // Domain
;;;649 1 << 4 |
;;;650 0x2; // Set as 1 Mbyte section
;;;651
;;;652 for(i = 0x200; i < 0xFFF; ++i)
000b08 e3a04c02 MOV r4,#0x200
000b0c ea000005 B |L1.2856|
|L1.2832|
;;;653 pTranslationTable[i] =
000b10 e3a00b01 MOV r0,#0x400
000b14 e1800a04 ORR r0,r0,r4,LSL #20
000b18 e3800c01 ORR r0,r0,#0x100
000b1c e38000f2 ORR r0,r0,#0xf2
000b20 e7830104 STR r0,[r3,r4,LSL #2]
000b24 e2844001 ADD r4,r4,#1 ;652
|L1.2856|
000b28 e59f0018 LDR r0,|L1.2888|
000b2c e1540000 CMP r4,r0 ;652
000b30 bafffff6 BLT |L1.2832|
;;;654 (i << 20) | // Physical Address
;;;655 (1 << 10) | // Access in supervisor mode
;;;656 (15 << 5) | // Domain
;;;657 1 << 4 |
;;;658 0x2; // Set as 1 Mbyte section
;;;659
;;;660 EnableMMU(); // Enable the MMU
000b34 ebfffffe BL EnableMMU
;;;661 }
000b38 e8bd4010 POP {r4,lr}
000b3c e12fff1e BX lr
;;;662
ENDP
__gccmain PROC
;;;672 {
;;;673 }
000b40 e12fff1e BX lr
ENDP
|L1.2884|
000b44 300005f2 DCD 0x300005f2
|L1.2888|
000b48 00000fff DCD 0x00000fff
AREA ||.data||, DATA, ALIGN=2
delayLoopCount
000000 000007ec DCD 0x000007ec
f_nWhichUart
000004 00000000 DCD 0x00000000
||Image$$RW_ZI$$ZI$$Limit||
000008 00 DCB 0x00
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