📄 2410lib.txt
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0002c4 ebfffffe BL __aeabi_i2d
0002c8 e58d0018 STR r0,[sp,#0x18]
0002cc e58d101c STR r1,[sp,#0x1c]
0002d0 e28f0f4b ADR r0,|L1.1028|
0002d4 e890000c LDM r0,{r2,r3}
0002d8 e59d0018 LDR r0,[sp,#0x18]
0002dc ebfffffe BL __aeabi_ddiv
0002e0 e58d0010 STR r0,[sp,#0x10]
0002e4 e58d1014 STR r1,[sp,#0x14]
0002e8 e59d2020 LDR r2,[sp,#0x20]
0002ec e59d3024 LDR r3,[sp,#0x24]
0002f0 ebfffffe BL __aeabi_ddiv
0002f4 e58d0008 STR r0,[sp,#8]
0002f8 e58d100c STR r1,[sp,#0xc]
0002fc e28f00d8 ADR r0,|L1.988|
000300 e890000c LDM r0,{r2,r3}
000304 e59d0008 LDR r0,[sp,#8]
000308 ebfffffe BL __aeabi_dadd
00030c e88d0003 STM sp,{r0,r1}
000310 ebfffffe BL __aeabi_d2iz
000314 e2400001 SUB r0,r0,#1
000318 e3a01205 MOV r1,#0x50000000
00031c e5810028 STR r0,[r1,#0x28]
;;;174 break;
000320 ea00005b B |L1.1172|
|L1.804|
;;;175
;;;176 case UART1:
000324 e1a00000 MOV r0,r0
;;;177 rUFCON1 = 0x0; //UART channel 1 FIFO control register, FIFO disable
000328 e3a00000 MOV r0,#0
00032c e59f10b0 LDR r1,|L1.996|
000330 e5810008 STR r0,[r1,#8]
;;;178 rUMCON1 = 0x0; //UART chaneel 1 MODEM control register, AFC disable
000334 e581000c STR r0,[r1,#0xc]
;;;179 rULCON1 = 0x3;
000338 e3a00003 MOV r0,#3
00033c e5810000 STR r0,[r1,#0]
;;;180 rUCON1 = 0x245;
000340 e59f00b8 LDR r0,|L1.1024|
000344 e5810004 STR r0,[r1,#4]
;;;181 rUBRDIV1=( (int)(nMainClk/16./nBaud) -1 );
000348 e1a00005 MOV r0,r5
00034c ebfffffe BL __aeabi_i2d
000350 e58d0020 STR r0,[sp,#0x20]
000354 e58d1024 STR r1,[sp,#0x24]
000358 e1a00004 MOV r0,r4
00035c ebfffffe BL __aeabi_i2d
000360 e58d0018 STR r0,[sp,#0x18]
000364 e58d101c STR r1,[sp,#0x1c]
000368 e28f0094 ADR r0,|L1.1028|
00036c e890000c LDM r0,{r2,r3}
000370 e59d0018 LDR r0,[sp,#0x18]
000374 ebfffffe BL __aeabi_ddiv
000378 e58d0010 STR r0,[sp,#0x10]
00037c e58d1014 STR r1,[sp,#0x14]
000380 e59d2020 LDR r2,[sp,#0x20]
000384 e59d3024 LDR r3,[sp,#0x24]
000388 ebfffffe BL __aeabi_ddiv
00038c e58d0008 STR r0,[sp,#8]
000390 e58d100c STR r1,[sp,#0xc]
000394 ebfffffe BL __aeabi_d2iz
000398 e2400001 SUB r0,r0,#1
00039c e59f1040 LDR r1,|L1.996|
0003a0 e5810028 STR r0,[r1,#0x28]
;;;182 break;
0003a4 ea00003a B |L1.1172|
|L1.936|
0003a8 005fbfff DCD 0x005fbfff
|L1.940|
0003ac 00155559 DCD 0x00155559
|L1.944|
0003b0 000007ff DCD 0x000007ff
|L1.948|
0003b4 aaaa55aa DCD 0xaaaa55aa
|L1.952|
0003b8 aaaaaaaa DCD 0xaaaaaaaa
|L1.956|
0003bc 0000ffff DCD 0x0000ffff
|L1.960|
0003c0 a6aaaaaa DCD 0xa6aaaaaa
|L1.964|
0003c4 000055aa DCD 0x000055aa
|L1.968|
0003c8 ff4af7b9 DCD 0xff4af7b9
|L1.972|
0003cc 0000ffcf DCD 0x0000ffcf
|L1.976|
0003d0 002aaaaa DCD 0x002aaaaa
|L1.980|
0003d4 00000000
0003d8 41482cf7 DCFD 0x41482cf700000000 ; 3168750
|L1.988|
0003dc 00000000
0003e0 3fe00000 DCFD 0x3fe0000000000000 ; 0.5
|L1.996|
0003e4 50004000 DCD 0x50004000
|L1.1000|
0003e8 50008000 DCD 0x50008000
|L1.1004|
0003ec 00000000 DCD ||.data||
|L1.1008|
0003f0 00003130 DCD 0x00003130
|L1.1012|
0003f4 00003110 DCD 0x00003110
|L1.1016|
0003f8 007a1200 DCD 0x007a1200
|L1.1020|
0003fc 03059ee0 DCD 0x03059ee0
|L1.1024|
000400 00000245 DCD 0x00000245
|L1.1028|
000404 00000000
000408 40300000 DCFD 0x4030000000000000 ; 16
|L1.1036|
;;;183
;;;184 case UART2:
00040c e1a00000 MOV r0,r0
;;;185 rULCON2 = 0x3;
000410 e3a00003 MOV r0,#3
000414 e51f1034 LDR r1,|L1.1000|
000418 e5810000 STR r0,[r1,#0]
;;;186 rUCON2 = 0x245;
00041c e51f0024 LDR r0,|L1.1024|
000420 e5810004 STR r0,[r1,#4]
;;;187 rUBRDIV2=( (int)(nMainClk/16./nBaud) -1 );
000424 e1a00005 MOV r0,r5
000428 ebfffffe BL __aeabi_i2d
00042c e58d0020 STR r0,[sp,#0x20]
000430 e58d1024 STR r1,[sp,#0x24]
000434 e1a00004 MOV r0,r4
000438 ebfffffe BL __aeabi_i2d
00043c e58d0018 STR r0,[sp,#0x18]
000440 e58d101c STR r1,[sp,#0x1c]
000444 e24f0048 ADR r0,|L1.1028|
000448 e890000c LDM r0,{r2,r3}
00044c e59d0018 LDR r0,[sp,#0x18]
000450 ebfffffe BL __aeabi_ddiv
000454 e58d0010 STR r0,[sp,#0x10]
000458 e58d1014 STR r1,[sp,#0x14]
00045c e59d2020 LDR r2,[sp,#0x20]
000460 e59d3024 LDR r3,[sp,#0x24]
000464 ebfffffe BL __aeabi_ddiv
000468 e58d0008 STR r0,[sp,#8]
00046c e58d100c STR r1,[sp,#0xc]
000470 ebfffffe BL __aeabi_d2iz
000474 e2400001 SUB r0,r0,#1
000478 e51f1098 LDR r1,|L1.1000|
00047c e5810028 STR r0,[r1,#0x28]
;;;188 rUFCON2 = 0x0; //UART channel 2 FIFO control register, FIFO disable
000480 e3a00000 MOV r0,#0
000484 e5810008 STR r0,[r1,#8]
;;;189 break;
000488 ea000001 B |L1.1172|
|L1.1164|
;;;190
;;;191 default:
00048c e1a00000 MOV r0,r0
;;;192 break;
000490 e1a00000 MOV r0,r0
|L1.1172|
000494 e1a00000 MOV r0,r0 ;174
;;;193 }
;;;194
;;;195 for(i=0;i<100;i++);
000498 e3a07000 MOV r7,#0
00049c ea000000 B |L1.1188|
|L1.1184|
0004a0 e2877001 ADD r7,r7,#1
|L1.1188|
0004a4 e3570064 CMP r7,#0x64
0004a8 bafffffc BLT |L1.1184|
;;;196 delay(400);
0004ac e3a00e19 MOV r0,#0x190
0004b0 ebfffffe BL delay
;;;197 }
0004b4 e28dd02c ADD sp,sp,#0x2c
0004b8 e8bd40f0 POP {r4-r7,lr}
0004bc e12fff1e BX lr
;;;198
ENDP
uart_select PROC
;;;208 {
;;;209 f_nWhichUart=nChannel;
0004c0 e59f1550 LDR r1,|L1.2584|
0004c4 e5810000 STR r0,[r1,#0] ; f_nWhichUart
;;;210 }
0004c8 e12fff1e BX lr
;;;211
ENDP
uart_txempty PROC
;;;221 {
;;;222 if(nChannel==0)
0004cc e3500000 CMP r0,#0
0004d0 1a000005 BNE |L1.1260|
;;;223 while(!(rUTRSTAT0 & 0x4)); //Wait until tx shifter is empty.
0004d4 e1a00000 MOV r0,r0
|L1.1240|
0004d8 e3a01205 MOV r1,#0x50000000
0004dc e5911010 LDR r1,[r1,#0x10]
0004e0 e3110004 TST r1,#4
0004e4 0afffffb BEQ |L1.1240|
0004e8 ea00000e B |L1.1320|
|L1.1260|
;;;224
;;;225 else if(nChannel==1)
0004ec e3500001 CMP r0,#1
0004f0 1a000005 BNE |L1.1292|
;;;226 while(!(rUTRSTAT1 & 0x4)); //Wait until tx shifter is empty.
0004f4 e1a00000 MOV r0,r0
|L1.1272|
0004f8 e51f111c LDR r1,|L1.996|
0004fc e5911010 LDR r1,[r1,#0x10]
000500 e3110004 TST r1,#4
000504 0afffffb BEQ |L1.1272|
000508 ea000006 B |L1.1320|
|L1.1292|
;;;227
;;;228 else if(nChannel==2)
00050c e3500002 CMP r0,#2
000510 1a000004 BNE |L1.1320|
;;;229 while(!(rUTRSTAT2 & 0x4)); //Wait until tx shifter is empty.
000514 e1a00000 MOV r0,r0
|L1.1304|
000518 e51f1138 LDR r1,|L1.1000|
00051c e5911010 LDR r1,[r1,#0x10]
000520 e3110004 TST r1,#4
000524 0afffffb BEQ |L1.1304|
|L1.1320|
;;;230 }
000528 e12fff1e BX lr
;;;231
ENDP
uart_getch PROC
;;;241 {
;;;242 if(f_nWhichUart==0)
00052c e59f04e4 LDR r0,|L1.2584|
000530 e5900000 LDR r0,[r0,#0] ; f_nWhichUart
000534 e3500000 CMP r0,#0
000538 1a000007 BNE |L1.1372|
;;;243 {
;;;244 while(!(rUTRSTAT0 & 0x1)); //Receive data ready
00053c e1a00000 MOV r0,r0
|L1.1344|
000540 e3a00205 MOV r0,#0x50000000
000544 e5900010 LDR r0,[r0,#0x10]
000548 e3100001 TST r0,#1
00054c 0afffffb BEQ |L1.1344|
;;;245 return RdURXH0();
000550 e3a00205 MOV r0,#0x50000000
000554 e5d00024 LDRB r0,[r0,#0x24]
|L1.1368|
;;;246 }
;;;247 else if(f_nWhichUart==1)
;;;248 {
;;;249 while(!(rUTRSTAT1 & 0x1)); //Receive data ready
;;;250 return RdURXH1();
;;;251 }
;;;252 else if(f_nWhichUart==2)
;;;253 {
;;;254 while(!(rUTRSTAT2 & 0x1)); //Receive data ready
;;;255 return RdURXH2();
;;;256 }
;;;257 return NULL;
;;;258 }
000558 e12fff1e BX lr
|L1.1372|
00055c e59f04b4 LDR r0,|L1.2584|
000560 e5900000 LDR r0,[r0,#0] ;247 ; f_nWhichUart
000564 e3500001 CMP r0,#1 ;247
000568 1a000007 BNE |L1.1420|
00056c e1a00000 MOV r0,r0 ;249
|L1.1392|
000570 e51f0194 LDR r0,|L1.996|
000574 e5900010 LDR r0,[r0,#0x10] ;249
000578 e3100001 TST r0,#1 ;249
00057c 0afffffb BEQ |L1.1392|
000580 e51f01a4 LDR r0,|L1.996|
000584 e5d00024 LDRB r0,[r0,#0x24] ;250
000588 eafffff2 B |L1.1368|
|L1.1420|
00058c e59f0484 LDR r0,|L1.2584|
000590 e5900000 LDR r0,[r0,#0] ;252 ; f_nWhichUart
000594 e3500002 CMP r0,#2 ;252
000598 1a000007 BNE |L1.1468|
00059c e1a00000 MOV r0,r0 ;254
|L1.1440|
0005a0 e51f01c0 LDR r0,|L1.1000|
0005a4 e5900010 LDR r0,[r0,#0x10] ;254
0005a8 e3100001 TST r0,#1 ;254
0005ac 0afffffb BEQ |L1.1440|
0005b0 e51f01d0 LDR r0,|L1.1000|
0005b4 e5d00024 LDRB r0,[r0,#0x24] ;255
0005b8 eaffffe6 B |L1.1368|
|L1.1468|
0005bc e3a00000 MOV r0,#0 ;257
0005c0 eaffffe4 B |L1.1368|
;;;259
ENDP
uart_getkey PROC
;;;269 {
;;;270 if(f_nWhichUart==0)
0005c4 e59f044c LDR r0,|L1.2584|
0005c8 e5900000 LDR r0,[r0,#0] ; f_nWhichUart
0005cc e3500000 CMP r0,#0
0005d0 1a000008 BNE |L1.1528|
;;;271 {
;;;272 if(rUTRSTAT0 & 0x1) //Receive data ready
0005d4 e3a00205 MOV r0,#0x50000000
0005d8 e5900010 LDR r0,[r0,#0x10]
0005dc e3100001 TST r0,#1
0005e0 0a000002 BEQ |L1.1520|
;;;273 return RdURXH0();
0005e4 e3a00205 MOV r0,#0x50000000
0005e8 e5d00024 LDRB r0,[r0,#0x24]
|L1.1516|
;;;274 else
;;;275 return 0;
;;;276 }
;;;277 else if(f_nWhichUart==1)
;;;278 {
;;;279 if(rUTRSTAT1 & 0x1) //Receive data ready
;;;280 return RdURXH1();
;;;281 else
;;;282 return 0;
;;;283 }
;;;284 else if(f_nWhichUart==2)
;;;285 {
;;;286 if(rUTRSTAT2 & 0x1) //Receive data ready
;;;287 return RdURXH2();
;;;288 else
;;;289 return 0;
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