📄 hal_nrf_l01.lst
字号:
300 {
301 1 return (bool)((hal_nrf_read_reg(FIFO_STATUS) >> RX_FULL) & 1);
302 1 }
303
304 bool hal_nrf_tx_fifo_empty(void)
305 {
306 1 return (bool)((hal_nrf_read_reg(FIFO_STATUS) >> TX_EMPTY) & 1);
307 1 }
308
309 bool hal_nrf_tx_fifo_full(void)
310 {
311 1 return (bool)((hal_nrf_read_reg(FIFO_STATUS) >> TX_FIFO_FULL) & 1);
312 1 }
313
314 uint8_t hal_nrf_get_tx_fifo_status(void)
315 {
316 1 return ((hal_nrf_read_reg(FIFO_STATUS) & ((1<<TX_FIFO_FULL)|(1<<TX_EMPTY))) >> 4);
317 1 }
318
319 uint8_t hal_nrf_get_rx_fifo_status(void)
320 {
321 1 return (hal_nrf_read_reg(FIFO_STATUS) & ((1<<RX_FULL)|(1<<RX_EMPTY)));
322 1 }
323
324 uint8_t hal_nrf_get_fifo_status(void)
325 {
326 1 return hal_nrf_read_reg(FIFO_STATUS);
327 1 }
328
329 uint8_t hal_nrf_get_transmit_attempts(void)
330 {
331 1 return hal_nrf_read_reg(OBSERVE_TX) & (BIT_3|BIT_2|BIT_1|BIT_0);
332 1 }
333
334 bool hal_nrf_get_carrier_detect(void)
335 {
336 1 return hal_nrf_read_reg(CD) & 1;
337 1 }
338
339 void hal_nrf_write_tx_pload(uint8_t *tx_pload, uint8_t length)
340 {
341 1 hal_nrf_write_multibyte_reg(UINT8(HAL_NRF_TX_PLOAD), tx_pload, length);
342 1 }
343
344 void hal_nrf_setup_dyn_pl(uint8_t setup)
345 {
346 1 hal_nrf_write_reg(DYNPD, setup & ~0xC0);
347 1 }
348
349 void hal_nrf_enable_dynamic_pl(void)
350 {
351 1 hal_nrf_write_reg(FEATURE, (hal_nrf_read_reg(FEATURE) | 0x04));
352 1 }
353
354 void hal_nrf_disable_dynamic_pl(void)
355 {
356 1 hal_nrf_write_reg(FEATURE, (hal_nrf_read_reg(FEATURE) & ~0x04));
357 1 }
358
359 void hal_nrf_enable_ack_pl(void)
360 {
361 1 hal_nrf_write_reg(FEATURE, (hal_nrf_read_reg(FEATURE) | 0x02));
C51 COMPILER V7.50 HAL_NRF_L01 04/09/2009 10:12:51 PAGE 7
362 1 }
363
364 void hal_nrf_disable_ack_pl(void)
365 {
366 1 hal_nrf_write_reg(FEATURE, (hal_nrf_read_reg(FEATURE) & ~0x02));
367 1 }
368
369 void hal_nrf_enable_dynamic_ack(void)
370 {
371 1 hal_nrf_write_reg(FEATURE, (hal_nrf_read_reg(FEATURE) | 0x01));
372 1 }
373
374 void hal_nrf_disable_dynamic_ack(void)
375 {
376 1 hal_nrf_write_reg(FEATURE, (hal_nrf_read_reg(FEATURE) & ~0x01));
377 1 }
378
379 void hal_nrf_write_ack_pload(uint8_t pipe, uint8_t *tx_pload, uint8_t length)
380 {
381 1 CSN_LOW();
382 1
383 1 hal_nrf_rw(WR_ACK_PLOAD | pipe);
384 1 while(length--)
385 1 {
386 2 hal_nrf_rw(*tx_pload++);
387 2 }
388 1
389 1 CSN_HIGH();
390 1 }
391
392 uint8_t hal_nrf_read_rx_pl_w()
393 {
394 1 uint8_t temp;
395 1
396 1 CSN_LOW();
397 1
398 1 hal_nrf_rw(RD_RX_PLOAD_W);
399 1 temp = hal_nrf_rw(0);
400 1 CSN_HIGH();
401 1
402 1 return temp;
403 1 }
404
405 void hal_nrf_lock_unlock()
406 {
407 1 CSN_LOW();
408 1
409 1 hal_nrf_rw(LOCK_UNLOCK);
410 1 hal_nrf_rw(0x73);
411 1
412 1 CSN_HIGH();
413 1 }
414
415 uint8_t hal_nrf_get_rx_data_source(void)
416 {
417 1 return ((hal_nrf_nop() & (BIT_3|BIT_2|BIT_1)) >> 1);
418 1 }
419
420 // Fixed: returns length==0 and pipe==7 means FIFO empty
421
422 uint16_t hal_nrf_read_rx_pload(uint8_t *rx_pload)
423 {
C51 COMPILER V7.50 HAL_NRF_L01 04/09/2009 10:12:51 PAGE 8
424 1 return hal_nrf_read_multibyte_reg(UINT8(HAL_NRF_RX_PLOAD), rx_pload);
425 1 }
426
427 void hal_nrf_reuse_tx(void)
428 {
429 1 hal_nrf_write_reg(REUSE_TX_PL, 0);
430 1 }
431
432 bool hal_nrf_get_reuse_tx_status(void)
433 {
434 1 return (bool)((hal_nrf_get_fifo_status() & (1<<TX_REUSE)) >> TX_REUSE);
435 1 }
436
437 void hal_nrf_flush_rx(void)
438 {
439 1 hal_nrf_write_reg(FLUSH_RX, 0);
440 1 }
441
442 void hal_nrf_flush_tx(void)
443 {
444 1 hal_nrf_write_reg(FLUSH_TX, 0);
445 1 }
446
447 uint8_t hal_nrf_nop(void)
448 {
449 1 return hal_nrf_write_reg(NOP,0);
450 1 }
451
452 void hal_nrf_set_pll_mode(hal_nrf_pll_mode_t pll_mode)
453 {
454 1 if(pll_mode == HAL_NRF_PLL_LOCK)
455 1 {
456 2 hal_nrf_write_reg(RF_SETUP, (hal_nrf_read_reg(RF_SETUP) | (1<<PLL_LOCK)));
457 2 }
458 1 else
459 1 {
460 2 hal_nrf_write_reg(RF_SETUP, (hal_nrf_read_reg(RF_SETUP) & ~(1<<PLL_LOCK)));
461 2 }
462 1 }
463
464 hal_nrf_pll_mode_t hal_nrf_get_pll_mode(void)
465 {
466 1 return (hal_nrf_pll_mode_t)((hal_nrf_read_reg(RF_SETUP) & (1<<PLL_LOCK)) >> PLL_LOCK);
467 1 }
468
469 void hal_nrf_set_lna_gain(hal_nrf_lna_mode_t lna_gain)
470 {
471 1 if(lna_gain == HAL_NRF_LNA_HCURR)
472 1 {
473 2 hal_nrf_write_reg(RF_SETUP, (hal_nrf_read_reg(RF_SETUP) | (1<<LNA_HCURR)));
474 2 }
475 1 else
476 1 {
477 2 hal_nrf_write_reg(RF_SETUP, (hal_nrf_read_reg(RF_SETUP) & ~(1<<LNA_HCURR)));
478 2 }
479 1 }
480
481 hal_nrf_lna_mode_t hal_nrf_get_lna_gain(void)
482 {
483 1 return (hal_nrf_lna_mode_t) ( (hal_nrf_read_reg(RF_SETUP) & (1<<LNA_HCURR)) >> LNA_HCURR );
484 1 }
485
C51 COMPILER V7.50 HAL_NRF_L01 04/09/2009 10:12:51 PAGE 9
486 uint8_t hal_nrf_read_reg(uint8_t reg)
487 {
488 1 uint8_t temp;
489 1 CSN_LOW();
490 1 hal_nrf_rw(reg);
491 1 temp = hal_nrf_rw(0);
492 1 CSN_HIGH();
493 1
494 1 return temp;
495 1 }
496
497 uint8_t hal_nrf_write_reg(uint8_t reg, uint8_t value)
498 {
499 1 uint8_t retval;
500 1 CSN_LOW();
501 1 if(reg < WRITE_REG) // i.e. this is a register access
502 1 {
503 2 retval = hal_nrf_rw(WRITE_REG + reg);
504 2 hal_nrf_rw(value);
505 2 }
506 1 else // single byte cmd OR future command/register access
507 1 {
508 2 if(!(reg == FLUSH_TX) && !(reg == FLUSH_RX) && !(reg == REUSE_TX_PL) && !(reg == NOP))
509 2 {
510 3 retval = hal_nrf_rw(reg);
511 3 hal_nrf_rw(value);
512 3 }
513 2 else // single byte L01 command
514 2 {
515 3 retval = hal_nrf_rw(reg);
516 3 }
517 2 }
518 1 CSN_HIGH();
519 1
520 1 return retval;
521 1 }
522
523 uint16_t hal_nrf_read_multibyte_reg(uint8_t reg, uint8_t *pbuf)
524 {
525 1 uint8_t ctr, length;
526 1 switch(reg)
527 1 {
528 2 case HAL_NRF_PIPE0:
529 2 case HAL_NRF_PIPE1:
530 2 case HAL_NRF_TX:
531 2 length = ctr = hal_nrf_get_address_width();
532 2 CSN_LOW();
533 2 hal_nrf_rw(RX_ADDR_P0 + reg);
534 2 break;
535 2
536 2 case HAL_NRF_RX_PLOAD:
537 2 if( (reg = hal_nrf_get_rx_data_source()) < 7)
538 2 {
539 3 length = ctr = hal_nrf_read_rx_pl_w();
540 3
541 3 CSN_LOW();
542 3 hal_nrf_rw(RD_RX_PLOAD);
543 3 }
544 2 else
545 2 {
546 3 ctr = length = 0;
547 3 }
C51 COMPILER V7.50 HAL_NRF_L01 04/09/2009 10:12:51 PAGE 10
548 2 break;
549 2
550 2 default:
551 2 ctr = length = 0;
552 2 break;
553 2 }
554 1
555 1 while(ctr--)
556 1 {
557 2 *pbuf++ = hal_nrf_rw(0);
558 2 }
559 1
560 1 CSN_HIGH();
561 1
562 1 return (((uint16_t) reg << 8) | length);
563 1 }
564
565 void hal_nrf_write_multibyte_reg(uint8_t reg, uint8_t *pbuf, uint8_t length)
566 {
567 1 switch(reg)
568 1 {
569 2 case HAL_NRF_PIPE0:
570 2 case HAL_NRF_PIPE1:
571 2 case HAL_NRF_TX:
572 2 length = hal_nrf_get_address_width();
573 2 CSN_LOW();
574 2 hal_nrf_rw(WRITE_REG + RX_ADDR_P0 + reg);
575 2 break;
576 2
577 2 case HAL_NRF_TX_PLOAD:
578 2 CSN_LOW();
579 2 hal_nrf_rw(WR_TX_PLOAD);
580 2 break;
581 2 default:
582 2 break;
583 2 }
584 1
585 1 while(length--)
586 1 {
587 2 hal_nrf_rw(*pbuf++);
588 2 }
589 1
590 1 CSN_HIGH();
591 1 }
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 1571 ----
CONSTANT SIZE = ---- ----
XDATA SIZE = ---- 36
PDATA SIZE = ---- ----
DATA SIZE = ---- ----
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
EDATA SIZE = ---- ----
HDATA SIZE = ---- ----
XDATA CONST SIZE = ---- ----
FAR CONST SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -