📄 test_maus.fit.rpt
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Fitter report for Test_maus
Tue Dec 09 10:44:33 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Pin-Out File
5. Fitter Resource Usage Summary
6. Input Pins
7. Output Pins
8. Bidir Pins
9. I/O Bank Usage
10. All Package Pins
11. PLL Summary
12. PLL Usage
13. Output Pin Default Load For Reported TCO
14. Fitter Resource Utilization by Entity
15. Delay Chain Summary
16. Pad To Core Delay Chain Fanout
17. Control Signals
18. Global & Other Fast Signals
19. Non-Global High Fan-Out Signals
20. Interconnect Usage Summary
21. LAB Logic Elements
22. LAB-wide Signals
23. LAB Signals Sourced
24. LAB Signals Sourced Out
25. LAB Distinct Inputs
26. Fitter Device Options
27. Operating Settings and Conditions
28. Fitter Messages
29. Fitter Suppressed Messages
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; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Fitter Summary ;
+------------------------------------+------------------------------------------+
; Fitter Status ; Successful - Tue Dec 09 10:44:33 2008 ;
; Quartus II Version ; 7.2 Build 151 09/26/2007 SJ Full Version ;
; Revision Name ; Test_maus ;
; Top-level Entity Name ; Test_maus ;
; Family ; Cyclone II ;
; Device ; EP2C35F672C6 ;
; Timing Models ; Final ;
; Total logic elements ; 264 / 33,216 ( < 1 % ) ;
; Total combinational functions ; 225 / 33,216 ( < 1 % ) ;
; Dedicated logic registers ; 169 / 33,216 ( < 1 % ) ;
; Total registers ; 169 ;
; Total pins ; 23 / 475 ( 5 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 483,840 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % ) ;
; Total PLLs ; 1 / 4 ( 25 % ) ;
+------------------------------------+------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option ; Setting ; Default Value ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device ; EP2C35F672C6 ; ;
; Fit Attempts to Skip ; 0 ; 0.0 ;
; Use smart compilation ; Off ; Off ;
; Maximum processors allowed for parallel compilation ; 1 ; 1 ;
; Use TimeQuest Timing Analyzer ; Off ; Off ;
; Router Timing Optimization Level ; Normal ; Normal ;
; Placement Effort Multiplier ; 1.0 ; 1.0 ;
; Router Effort Multiplier ; 1.0 ; 1.0 ;
; Always Enable Input Buffers ; Off ; Off ;
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