📄 fet430_ta01.asm
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;*******************************************************************************
; MSP-FET430P430 Demo - Timer_A Toggle P5.1, CCR0 Contmode ISR, DCO SMCLK
;
; Description; Toggle P5.1 using using software and TA_0 ISR. Toggle rate is
; set at 50000 DCO/SMCLK cycles. Default DCO frequency used for TACLK.
; During the TA_0 ISR P5.1 is toggled and 50000 clock cycles are added to
; CCR0. TA_0 ISR is triggered exactly 50000 cycles. CPU is normally off and
; used only during TA_ISR.
; ACLK = n/a, MCLK = SMCLK = TACLK = default DCO
;
; MSP430FG439
; -----------------
; /|\| XIN|-
; | | |
; --|RST XOUT|-
; | |
; | P5.1|-->LED
;
; M.Buccini
; Texas Instruments, Inc
; September 2004
; Built with CCE for MSP430 Version: 1.00
;*******************************************************************************
.cdecls C,LIST,"msp430xG43x.h" ; Include device header file
;-------------------------------------------------------------------------------
.text ; Progam Start
;-------------------------------------------------------------------------------
RESET mov.w #0A00h,SP ; Initialize stack pointer
StopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop WDT
SetupP5 bis.b #002h,&P5DIR ; P5.1 output
SetupC0 mov.w #CCIE,&CCTL0 ; CCR0 interrupt enabled
mov.w #50000,&CCR0 ;
SetupTA mov.w #TASSEL_2+MC_2,&TACTL ; SMCLK, contmode
;
Mainloop bis.w #CPUOFF+GIE,SR ; CPU off, interrupts enabled
nop ; Required for debugger
;
;-------------------------------------------------------------------------------
TA0_ISR; Toggle P5.1
;-------------------------------------------------------------------------------
xor.b #002h,&P5OUT ; Toggle P5.1
add.w #50000,&CCR0 ; Add Offset to CCR0
reti ;
;
;------------------------------------------------------------------------------
; Interrupt Vectors
;------------------------------------------------------------------------------
.sect ".reset" ; MSP430 RESET Vector
.short RESET ;
.sect ".int06" ; Timer_A0 Vector
.short TA0_ISR ;
.end
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