📄 2440addr.h
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/**************************************************************************/
/* */
/* only for 32bit mode and dosn't support interrupt nesting */
/* */
/* File name: threadX_cpu.c */
/* Last modified Date: 2008-03-28 */
/* Last Version: 0.01 */
/* Descriptions: */
/* QQ: 307102293 */
/* ENAIL: wodexinxiang1949@163.com */
/* */
/**************************************************************************/
#ifndef __2440ADDR_H
#define __2440ADDR_H
/*********************************************************************************************************
C++ 兼容声明
*********************************************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/*********************************************************************************************************
存储器控制
*********************************************************************************************************/
#define rBWSCON (*(volatile unsigned *)0x48000000) /* Bus width & wait status */
#define rBANKCON0 (*(volatile unsigned *)0x48000004) /* Boot ROM control */
#define rBANKCON1 (*(volatile unsigned *)0x48000008) /* BANK1 control */
#define rBANKCON2 (*(volatile unsigned *)0x4800000c) /* BANK2 cControl */
#define rBANKCON3 (*(volatile unsigned *)0x48000010) /* BANK3 control */
#define rBANKCON4 (*(volatile unsigned *)0x48000014) /* BANK4 control */
#define rBANKCON5 (*(volatile unsigned *)0x48000018) /* BANK5 control */
#define rBANKCON6 (*(volatile unsigned *)0x4800001c) /* BANK6 control */
#define rBANKCON7 (*(volatile unsigned *)0x48000020) /* BANK7 control */
#define rREFRESH (*(volatile unsigned *)0x48000024) /* DRAM/SDRAM refresh */
#define rBANKSIZE (*(volatile unsigned *)0x48000028) /* Flexible Bank Size */
#define rMRSRB6 (*(volatile unsigned *)0x4800002c) /* Mode register set for SDRAM */
#define rMRSRB7 (*(volatile unsigned *)0x48000030) /* Mode register set for SDRAM */
/*********************************************************************************************************
USB 主控器 (OHCI Rev 1.0 compatible)
*********************************************************************************************************/
#define rHcRevision (*(volatile unsigned *)0x49000000)
#define rHcControl (*(volatile unsigned *)0x49000004)
#define rHcCommonStatus (*(volatile unsigned *)0x49000008)
#define rHcInterruptStatus (*(volatile unsigned *)0x4900000C)
#define rHcInterruptEnable (*(volatile unsigned *)0x49000010)
#define rHcInterruptDisable (*(volatile unsigned *)0x49000014)
#define rHcHCCA (*(volatile unsigned *)0x49000018)
#define rHcPeriodCuttentED (*(volatile unsigned *)0x4900001C)
#define rHcControlHeadED (*(volatile unsigned *)0x49000020)
#define rHcControlCurrentED (*(volatile unsigned *)0x49000024)
#define rHcBulkHeadED (*(volatile unsigned *)0x49000028)
#define rHcBulkCurrentED (*(volatile unsigned *)0x4900002C)
#define rHcDoneHead (*(volatile unsigned *)0x49000030)
#define rHcRmInterval (*(volatile unsigned *)0x49000034)
#define rHcFmRemaining (*(volatile unsigned *)0x49000038)
#define rHcFmNumber (*(volatile unsigned *)0x4900003C)
#define rHcPeriodicStart (*(volatile unsigned *)0x49000040)
#define rHcLSThreshold (*(volatile unsigned *)0x49000044)
#define rHcRhDescriptorA (*(volatile unsigned *)0x49000048)
#define rHcRhDescriptorB (*(volatile unsigned *)0x4900004C)
#define rHcRhStatus (*(volatile unsigned *)0x49000050)
#define rHcRhPortStatus1 (*(volatile unsigned *)0x49000054)
#define rHcRhPortStatus2 (*(volatile unsigned *)0x49000058)
/*********************************************************************************************************
INTERRUPT CONTROLER
*********************************************************************************************************/
#define rSRCPND (*(volatile unsigned *)0x4a000000) /* Interrupt request status */
#define rINTMOD (*(volatile unsigned *)0x4a000004) /* Interrupt mode control */
#define rINTMSK (*(volatile unsigned *)0x4a000008) /* Interrupt mask control */
#define rPRIORITY (*(volatile unsigned *)0x4a00000c) /* IRQ priority control */
#define rINTPND (*(volatile unsigned *)0x4a000010) /* Interrupt request status */
#define rINTOFFSET (*(volatile unsigned *)0x4a000014) /* Interruot request source */
/* offset */
#define rSUBSRCPND (*(volatile unsigned *)0x4a000018) /* Sub source pending */
#define rINTSUBMSK (*(volatile unsigned *)0x4a00001c) /* Interrupt sub mask */
/*********************************************************************************************************
DMA CONTROLER
*********************************************************************************************************/
#define rDISRC0 (*(volatile unsigned *)0x4b000000) /* DMA 0 Initial source */
#define rDISRCC0 (*(volatile unsigned *)0x4b000004) /* DMA 0 Initial source control*/
#define rDIDST0 (*(volatile unsigned *)0x4b000008) /* DMA 0 Initial Destination */
#define rDIDSTC0 (*(volatile unsigned *)0x4b00000c) /* DMA 0 Initial Destination */
/* control */
#define rDCON0 (*(volatile unsigned *)0x4b000010) /* DMA 0 Control */
#define rDSTAT0 (*(volatile unsigned *)0x4b000014) /* DMA 0 Status */
#define rDCSRC0 (*(volatile unsigned *)0x4b000018) /* DMA 0 Current source */
#define rDCDST0 (*(volatile unsigned *)0x4b00001c) /* DMA 0 Current destination */
#define rDMASKTRIG0 (*(volatile unsigned *)0x4b000020) /* DMA 0 Mask trigger */
#define rDISRC1 (*(volatile unsigned *)0x4b000040) /* DMA 1 Initial source */
#define rDISRCC1 (*(volatile unsigned *)0x4b000044) /* DMA 1 Initial source control*/
#define rDIDST1 (*(volatile unsigned *)0x4b000048) /* DMA 1 Initial Destination */
#define rDIDSTC1 (*(volatile unsigned *)0x4b00004c) /* DMA 1 Initial Destination */
/* control */
#define rDCON1 (*(volatile unsigned *)0x4b000050) /* DMA 1 Control */
#define rDSTAT1 (*(volatile unsigned *)0x4b000054) /* DMA 1 Status */
#define rDCSRC1 (*(volatile unsigned *)0x4b000058) /* DMA 1 Current source */
#define rDCDST1 (*(volatile unsigned *)0x4b00005c) /* DMA 1 Current destination */
#define rDMASKTRIG1 (*(volatile unsigned *)0x4b000060) /* DMA 1 Mask trigger */
#define rDISRC2 (*(volatile unsigned *)0x4b000080) /* DMA 2 Initial source */
#define rDISRCC2 (*(volatile unsigned *)0x4b000084) /* DMA 2 Initial source control*/
#define rDIDST2 (*(volatile unsigned *)0x4b000088) /* DMA 2 Initial Destination */
#define rDIDSTC2 (*(volatile unsigned *)0x4b00008c) /* DMA 2 Initial Destination */
/* control */
#define rDCON2 (*(volatile unsigned *)0x4b000090) /* DMA 2 Control */
#define rDSTAT2 (*(volatile unsigned *)0x4b000094) /* DMA 2 Status */
#define rDCSRC2 (*(volatile unsigned *)0x4b000098) /* DMA 2 Current source */
#define rDCDST2 (*(volatile unsigned *)0x4b00009c) /* DMA 2 Current destination */
#define rDMASKTRIG2 (*(volatile unsigned *)0x4b0000a0) /* DMA 2 Mask trigger */
#define rDISRC3 (*(volatile unsigned *)0x4b0000c0) /* DMA 3 Initial source */
#define rDISRCC3 (*(volatile unsigned *)0x4b0000c4) /* DMA 3 Initial source control*/
#define rDIDST3 (*(volatile unsigned *)0x4b0000c8) /* DMA 3 Initial Destination */
#define rDIDSTC3 (*(volatile unsigned *)0x4b0000cc) /* DMA 3 Initial Destination */
/* control */
#define rDCON3 (*(volatile unsigned *)0x4b0000d0) /* DMA 3 Control */
#define rDSTAT3 (*(volatile unsigned *)0x4b0000d4) /* DMA 3 Status */
#define rDCSRC3 (*(volatile unsigned *)0x4b0000d8) /* DMA 3 Current source */
#define rDCDST3 (*(volatile unsigned *)0x4b0000dc) /* DMA 3 Current destination */
#define rDMASKTRIG3 (*(volatile unsigned *)0x4b0000e0) /* DMA 3 Mask trigger */
/*********************************************************************************************************
CLOCK & POWER MANAGEMENT
*********************************************************************************************************/
#define rLOCKTIME (*(volatile unsigned *)0x4c000000) /* PLL lock time counter */
#define rMPLLCON (*(volatile unsigned *)0x4c000004) /* MPLL Control */
#define rUPLLCON (*(volatile unsigned *)0x4c000008) /* UPLL Control */
#define rCLKCON (*(volatile unsigned *)0x4c00000c) /* Clock generator control */
#define rCLKSLOW (*(volatile unsigned *)0x4c000010) /* Slow clock control */
#define rCLKDIVN (*(volatile unsigned *)0x4c000014) /* Clock divider control */
#define rCAMDIVN (*(volatile unsigned *)0x4c000018) /* USB, CAM Clock divider */
/* control */
/*********************************************************************************************************
LCD CONTROLLER
*********************************************************************************************************/
#define rLCDCON1 (*(volatile unsigned *)0x4d000000) /* LCD control 1 */
#define rLCDCON2 (*(volatile unsigned *)0x4d000004) /* LCD control 2 */
#define rLCDCON3 (*(volatile unsigned *)0x4d000008) /* LCD control 3 */
#define rLCDCON4 (*(volatile unsigned *)0x4d00000c) /* LCD control 4 */
#define rLCDCON5 (*(volatile unsigned *)0x4d000010) /* LCD control 5 */
#define rLCDSADDR1 (*(volatile unsigned *)0x4d000014) /* STN/TFT Frame buffer start */
/* address 1 */
#define rLCDSADDR2 (*(volatile unsigned *)0x4d000018) /* STN/TFT Frame buffer start */
/* address 2 */
#define rLCDSADDR3 (*(volatile unsigned *)0x4d00001c) /* STN/TFT Virtual screen */
/* address set */
#define rREDLUT (*(volatile unsigned *)0x4d000020) /* STN Red lookup table */
#define rGREENLUT (*(volatile unsigned *)0x4d000024) /* STN Green lookup table */
#define rBLUELUT (*(volatile unsigned *)0x4d000028) /* STN Blue lookup table */
#define rDITHMODE (*(volatile unsigned *)0x4d00004c) /* STN Dithering mode */
#define rTPAL (*(volatile unsigned *)0x4d000050) /* TFT Temporary palette */
#define rLCDINTPND (*(volatile unsigned *)0x4d000054) /* LCD Interrupt pending */
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