📄 startup.s
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;/* DATE NAME DESCRIPTION */
;/* */
;/* */
;/**************************************************************************/
__user_initial_stackheap FUNCTION
LDR r0, =bottom_of_heap
MOV pc, lr
ENDFUNC
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* TargetInitReset */
;/* 3.0a */
;/* AUTHOR */
;/* */
;/* */
;/* */
;/* DESCRIPTION */
;/* */
;/* config the data bus, resert watch dog, and initialize the clock */
;/* */
;/* INPUT */
;/* */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* resert handle */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* */
;/**************************************************************************/
TargetInitReset FUNCTION
LDR R0, =WTCON
; close the watch dog
MOV R1, #0
STR R1, [R0]
LDR R0, =INTMSK
; mask all interrupu source
LDR R1, =0xFFFFFFFF
STR R1, [R0]
LDR R0, =INTSUBMSK
LDR R1, =0x07FF
STR R1, [R0]
LDR R0, =SRCPND
LDR R1, =0xFFFFFFFF
; clear all interrupt flag
STR R1, [R0]
LDR R0, =INTPND
LDR R1, [R0]
STR R1, [R0]
;
; 总线设置,初始化SDRAM
;
LDR R0, =BUS_INIT
LDR R1, =BWSCON
LDMIA R0!, {R2-R8}
STMIA R1!, {R2-R8}
LDMIA R0!, {R2-R7}
STMIA R1!, {R2-R7}
LDR R0, =CAMDIVN
LDR R1, =0
STR R1, [R0]
;
; 拷贝向量表
;
;LDR R0, =0X30000000
;MOV R1, #0X00000000
;LDMIA R0!, {R2-R9}
;STMIA R1!, {R2-R9}
;LDMIA R0!, {R2-R9}
;STMIA R1!, {R2-R9}
;
; 系统时钟设置,启用PLL
; LOCKTIME = 0x00FFFFFF, 锁定时间设置U_LTIME=0xFFF,M_LTIME=0xFFF
; FCLK : HCLK : PCLK = 1 : 4 : 8
;
LDR R0, =CLKDIVN
LDR R1, =(0 << 3) | (2 << 1) | 1
STR R1, [R0]
LDR R0, =CAMDIVN
LDR R1, =0
STR R1, [R0]
LDR R0, =MPLLCON
LDR R1, =(127 << 12) | (2 << 4) | 1
STR R1, [R0]
LDR R0, =UPLLCON
LDR R1, =(56 << 12) | (2 << 4) | 2
STR R1, [R0]
LDR R0, =LOCKTIME
LDR R1, =0x00FFFFFF
STR R1, [R0]
MOV PC, LR
ENDFUNC
BUS_INIT
DCD ((B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ;GCS0
DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ;GCS1
DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ;GCS2
DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ;GCS3
DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ;GCS4
DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ;GCS5
DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ;GCS6
DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ;GCS7
DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Tsrc<<18)+REFCNT)
DCD 0xb2 ;SCLK power saving mode, ARM core burst enable , BANKSIZE 128M/128M - 11/29/2002
DCD 0x30 ;MRSR6 CL=3clk
DCD 0x30 ;MRSR7
;/**************************************************************************/
;/* end of file */
;/**************************************************************************/
END
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