time_div.vhd

IP 分频器 可以通过输入参数而自动调整分频数

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-- Company: 
-- Engineer: 
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-- Create Date:    22:50:24 10/07/2008 
-- Design Name: 
-- Module Name:    time_div - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
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-- Dependencies: 
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-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity time_div is
	 generic(
			 CNT:integer:=25000);   --set divide number
    Port ( 
    			 clkin  :  in     STD_LOGIC;
			 rst_n  :  in     STD_LOGIC;
          clkout :  out    STD_LOGIC);
end time_div;

architecture Behavioral of time_div is
signal clktmp:std_logic:='0';
begin
process(clkin,rst_n)
variable counter:integer range 0 to CNT;
begin
	if(rst_n = '0')then
		counter := 0;
		clktmp <= '0';
	elsif(clkin'event and clkin = '1')then
		if(counter = CNT-1)then      --counter is full flip the output
			counter := 0;
			clktmp <= not clktmp;      --output
		else
			counter := counter + 1;     --counter is accumlate
		end if;
	end if;
end process;
clkout <= clktmp;
end Behavioral;