lab1.v.bak

My first project written in Quartus II by using VHDL, executed some tasks that display word on 7-seg

module lab1(SW,HEX0,HEX1,HEX2,HEX3,HEX4);
    input  [17:0] SW;
    output [0:6]  HEX0,HEX1,HEX2,HEX3,HEX4;
    wire   [2:0]  Ma,Mb,Mc,Md,Me,Mf,Mg,Mh;

    mux_3bit_5tol M0(SW[17:15], SW[14:12], SW[11:9], SW[8:6], SW[5:3], SW[2:0], Ma,Mb,Mc,Md,Me);
	
	
    
    char_7seg H0(Me, HEX3);
    char_7seg H1(Md, HEX4);
    char_7seg H2(Mc, HEX5);
    char_7seg H3(Mb, HEX6);
    char_7seg H4(Ma, HEX7);
    
    
endmodule


module mux_3bit_5tol(S,U,V,W,X,Y,Ma,Mb,Mc,Md,Me);
	
    input [2:0]S,U,V,W,X,Y;
    
    output [2:0]Ma,Mb,Mc,Md,Me;
    
    assign Ma[2] = (~S[2] &((~S[1] & ((~S[0] & U[2]) | (S[0] & V[2]))) | (S[1] & ((~S[0] & W[2]) | (S[0] & X[2]))))) | (S[2] & Y[2]) ;
	assign Ma[1] = (~S[2] &((~S[1] & ((~S[0] & U[1]) | (S[0] & V[1]))) | (S[1] & ((~S[0] & W[1]) | (S[0] & X[1]))))) | (S[2] & Y[1]) ;
	assign Ma[0] = (~S[2] &((~S[1] & ((~S[0] & U[0]) | (S[0] & V[0]))) | (S[1] & ((~S[0] & W[0]) | (S[0] & X[0]))))) | (S[2] & Y[0]) ;
    
    assign Mb[2] = (~S[2] &((~S[1] & ((~S[0] & V[2]) | (S[0] & W[2]))) | (S[1] & ((~S[0] & X[2]) | (S[0] & Y[2]))))) | (S[2] & U[2]) ;
	assign Mb[1] = (~S[2] &((~S[1] & ((~S[0] & V[1]) | (S[0] & W[1]))) | (S[1] & ((~S[0] & X[1]) | (S[0] & Y[1]))))) | (S[2] & U[1]) ;
	assign Mb[0] = (~S[2] &((~S[1] & ((~S[0] & V[0]) | (S[0] & W[0]))) | (S[1] & ((~S[0] & X[0]) | (S[0] & Y[0]))))) | (S[2] & U[0]) ;
    
    assign Mc[2] = (~S[2] &((~S[1] & ((~S[0] & W[2]) | (S[0] & X[2]))) | (S[1] & ((~S[0] & Y[2]) | (S[0] & U[2]))))) | (S[2] & V[2]) ;
	assign Mc[1] = (~S[2] &((~S[1] & ((~S[0] & W[1]) | (S[0] & X[1]))) | (S[1] & ((~S[0] & Y[1]) | (S[0] & U[1]))))) | (S[2] & V[1]) ;
	assign Mc[0] = (~S[2] &((~S[1] & ((~S[0] & W[0]) | (S[0] & X[0]))) | (S[1] & ((~S[0] & Y[0]) | (S[0] & U[0]))))) | (S[2] & V[0]) ;
	
	assign Md[2] = (~S[2] &((~S[1] & ((~S[0] & X[2]) | (S[0] & Y[2]))) | (S[1] & ((~S[0] & U[2]) | (S[0] & V[2]))))) | (S[2] & W[2]) ;
	assign Md[1] = (~S[2] &((~S[1] & ((~S[0] & X[1]) | (S[0] & Y[1]))) | (S[1] & ((~S[0] & U[1]) | (S[0] & V[1]))))) | (S[2] & W[1]) ;
	assign Md[0] = (~S[2] &((~S[1] & ((~S[0] & X[0]) | (S[0] & Y[0]))) | (S[1] & ((~S[0] & U[0]) | (S[0] & V[0]))))) | (S[2] & W[0]) ;
	
	assign Me[2] = (~S[2] &((~S[1] & ((~S[0] & Y[2]) | (S[0] & U[2]))) | (S[1] & ((~S[0] & V[2]) | (S[0] & W[2]))))) | (S[2] & X[2]) ;
	assign Me[1] = (~S[2] &((~S[1] & ((~S[0] & Y[1]) | (S[0] & U[1]))) | (S[1] & ((~S[0] & V[1]) | (S[0] & W[1]))))) | (S[2] & X[1]) ;
	assign Me[0] = (~S[2] &((~S[1] & ((~S[0] & Y[0]) | (S[0] & U[0]))) | (S[1] & ((~S[0] & V[0]) | (S[0] & W[0]))))) | (S[2] & X[0]) ;
	
	
endmodule


module char_7seg(C, Display);
    input  [2:0] C; 
    output [0:6] Display;
    
    assign Display[6] = ~(~C[2] & ~C[1]);
    assign Display[5] = ~(C[2] | ~C[2]);
    assign Display[4] = ~(C[2] | ~C[2]);
    assign Display[3] = ~((~C[2] & ~C[1] & C[0]) | (~C[2] & C[1] & ~C[0]) | (~C[2] & C[1] & C[0]) | (C[2] & ~C[1] & ~C[0]) );
    assign Display[2] = ~((~C[1] & ~C[0]) | (C[1] & C[0]));
    assign Display[1] = ~((~C[1] & ~C[0]) | (C[1] & C[0]));
    assign Display[0] = ~(((~C[2] & ~C[1]) & (~C[1] & C[0])) | ((C[2] & ~C[1]) & (~C[1] & ~C[0])));
    
endmodule