lab1.tan.rpt

My first project written in Quartus II by using VHDL, executed some tasks that display word on 7-seg

Classic Timing Analyzer report for lab1
Tue May 12 15:51:28 2009
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                      ;
+------------------------------+-------+---------------+-------------+--------+---------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From   ; To      ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+--------+---------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 15.246 ns   ; SW[15] ; HEX1[0] ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;        ;         ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+--------+---------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                   ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                   ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                          ; Near End           ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; tpd                                                                                                                                ;
+-----------------------------------------+-----------------------------------------------------+-----------------+--------+---------+
; Slack                                   ; Required P2P Time                                   ; Actual P2P Time ; From   ; To      ;
+-----------------------------------------+-----------------------------------------------------+-----------------+--------+---------+
; N/A                                     ; None                                                ; 15.246 ns       ; SW[15] ; HEX1[0] ;
; N/A                                     ; None                                                ; 15.120 ns       ; SW[15] ; HEX4[0] ;
; N/A                                     ; None                                                ; 15.120 ns       ; SW[15] ; HEX4[1] ;
; N/A                                     ; None                                                ; 15.120 ns       ; SW[15] ; HEX4[2] ;
; N/A                                     ; None                                                ; 14.929 ns       ; SW[15] ; HEX1[3] ;
; N/A                                     ; None                                                ; 14.744 ns       ; SW[15] ; HEX2[3] ;
; N/A                                     ; None                                                ; 14.689 ns       ; SW[17] ; HEX1[0] ;
; N/A                                     ; None                                                ; 14.658 ns       ; SW[15] ; HEX2[6] ;
; N/A                                     ; None                                                ; 14.631 ns       ; SW[14] ; HEX1[0] ;
; N/A                                     ; None                                                ; 14.620 ns       ; SW[16] ; HEX1[0] ;
; N/A                                     ; None                                                ; 14.585 ns       ; SW[14] ; HEX4[0] ;
; N/A                                     ; None                                                ; 14.472 ns       ; SW[14] ; HEX1[6] ;
; N/A                                     ; None                                                ; 14.461 ns       ; SW[16] ; HEX1[6] ;
; N/A                                     ; None                                                ; 14.455 ns       ; SW[15] ; HEX1[2] ;
; N/A                                     ; None                                                ; 14.425 ns       ; SW[15] ; HEX4[3] ;
; N/A                                     ; None                                                ; 14.407 ns       ; SW[15] ; HEX0[0] ;
; N/A                                     ; None                                                ; 14.399 ns       ; SW[15] ; HEX1[6] ;
; N/A                                     ; None                                                ; 14.390 ns       ; SW[17] ; HEX4[0] ;
; N/A                                     ; None                                                ; 14.390 ns       ; SW[17] ; HEX4[1] ;
; N/A                                     ; None                                                ; 14.390 ns       ; SW[17] ; HEX4[2] ;
; N/A                                     ; None                                                ; 14.372 ns       ; SW[17] ; HEX1[3] ;
; N/A                                     ; None                                                ; 14.361 ns       ; SW[17] ; HEX1[6] ;