lab1.map.rpt

My first project written in Quartus II by using VHDL, executed some tasks that display word on 7-seg

; Auto Gated Clock Conversion                                    ; Off                ; Off                ;
; Block Design Naming                                            ; Auto               ; Auto               ;
; SDC constraint protection                                      ; Off                ; Off                ;
; Synthesis Effort                                               ; Auto               ; Auto               ;
; Allows Asynchronous Clear Usage For Shift Register Replacement ; On                 ; On                 ;
; Analysis & Synthesis Message Level                             ; Medium             ; Medium             ;
+----------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                         ;
+----------------------------------+-----------------+------------------------+------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                                     ;
+----------------------------------+-----------------+------------------------+------------------------------------------------------------------+
; lab1.v                           ; yes             ; User Verilog HDL File  ; C:/Documents and Settings/Khang/Desktop/TTTN/project/Lab1/lab1.v ;
+----------------------------------+-----------------+------------------------+------------------------------------------------------------------+


+------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary          ;
+---------------------------------------------+--------+
; Resource                                    ; Usage  ;
+---------------------------------------------+--------+
; Estimated Total logic elements              ; 66     ;
;                                             ;        ;
; Total combinational functions               ; 66     ;
; Logic element usage by number of LUT inputs ;        ;
;     -- 4 input functions                    ; 25     ;
;     -- 3 input functions                    ; 40     ;
;     -- <=2 input functions                  ; 1      ;
;                                             ;        ;
; Logic elements by mode                      ;        ;
;     -- normal mode                          ; 66     ;
;     -- arithmetic mode                      ; 0      ;
;                                             ;        ;
; Total registers                             ; 0      ;
;     -- Dedicated logic registers            ; 0      ;
;     -- I/O registers                        ; 0      ;
;                                             ;        ;
; I/O pins                                    ; 53     ;
; Maximum fan-out node                        ; SW[17] ;
; Maximum fan-out                             ; 40     ;
; Total fan-out                               ; 247    ;
; Average fan-out                             ; 2.08   ;
+---------------------------------------------+--------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                            ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name    ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------+--------------+
; |lab1                      ; 66 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 53   ; 0            ; |lab1                  ; work         ;
;    |char_7seg:H0|          ; 5 (5)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab1|char_7seg:H0     ; work         ;
;    |char_7seg:H1|          ; 4 (4)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab1|char_7seg:H1     ; work         ;
;    |char_7seg:H2|          ; 4 (4)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab1|char_7seg:H2     ; work         ;
;    |char_7seg:H3|          ; 4 (4)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab1|char_7seg:H3     ; work         ;
;    |char_7seg:H4|          ; 4 (4)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab1|char_7seg:H4     ; work         ;
;    |mux_3bit_5tol:M0|      ; 45 (45)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab1|mux_3bit_5tol:M0 ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
; 3:1                ; 15 bits   ; 30 LEs        ; 30 LEs               ; 0 LEs                  ; No         ; |lab1|mux_3bit_5tol:M0|Mc[0] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition
    Info: Processing started: Tue May 12 15:51:07 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lab1 -c lab1
Info: Found 3 design units, including 3 entities, in source file lab1.v
    Info: Found entity 1: lab1
    Info: Found entity 2: mux_3bit_5tol
    Info: Found entity 3: char_7seg
Info: Elaborating entity "lab1" for the top level hierarchy
Info: Elaborating entity "mux_3bit_5tol" for hierarchy "mux_3bit_5tol:M0"
Info: Elaborating entity "char_7seg" for hierarchy "char_7seg:H0"
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "HEX0[5]" is stuck at GND
    Warning (13410): Pin "HEX0[4]" is stuck at GND
    Warning (13410): Pin "HEX1[5]" is stuck at GND
    Warning (13410): Pin "HEX1[4]" is stuck at GND
    Warning (13410): Pin "HEX2[5]" is stuck at GND
    Warning (13410): Pin "HEX2[4]" is stuck at GND
    Warning (13410): Pin "HEX3[5]" is stuck at GND
    Warning (13410): Pin "HEX3[4]" is stuck at GND
    Warning (13410): Pin "HEX4[5]" is stuck at GND
    Warning (13410): Pin "HEX4[4]" is stuck at GND
Info: Implemented 119 device resources after synthesis - the final resource count might be different
    Info: Implemented 18 input pins
    Info: Implemented 35 output pins
    Info: Implemented 66 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings
    Info: Peak virtual memory: 164 megabytes
    Info: Processing ended: Tue May 12 15:51:10 2009
    Info: Elapsed time: 00:00:03
    Info: Total CPU time (on all processors): 00:00:03