📄 main.lst
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153 //
154 // If there is a network connection, the function returns 1.
155 //
156 // In the call to mn_ether_init(), NUM_AUTONEG_ATTEMPTS is set to 0, so the
157 // function will not return until it successfully auto-negotiates.
158 //
159 // mn_ether_init() will not be a blocking call if NUM_AUTONEG_ATTEMPTS is set
160 // to a value greater than 0.
161 //
162 int establish_network_connection()
163 {
164 1 int retval;
165 1
166 1 do
167 1 {
168 2 // mn_ether_init() initializes the Ethernet controller.
169 2 // AUTO_NEG indicates that the controller will auto-negotiate.
170 2 retval = mn_ether_init(AUTO_NEG, 0, 0);
171 2
172 2 // If there is no link, poll link_status until it sets or the
173 2 // CP2200 resets and then call mn_ether_init() again.
174 2 if (retval == LINK_FAIL)
175 2 {
176 3 while(!link_status && !ether_reset);
177 3 }
178 2
C51 COMPILER V8.08 MAIN 04/01/2008 20:10:55 PAGE 4
179 2 // If retval is less than zero and is not LINK_FAIL, there is a
180 2 // hardware error.
181 2 else if (retval < 0)
182 2 {
183 3 // Verify that the Ethernet controller is connected and powered properly.
184 3 // Verity that the EMIF has been configured at a speed compatible with the
185 3 // Ethernet controller.
186 3 while(1);
187 3 }
188 2
189 2 }while(retval < 0);
190 1
191 1 return (1);
192 1
193 1 }
194
195
196 //-----------------------------------------------------------------------------
197 // Initialization Routines
198 //-----------------------------------------------------------------------------
199
200 //-----------------------------------------------------------------------------
201 // PORT_Init
202 //-----------------------------------------------------------------------------
203 //
204 // Configure the Interrupts, Crossbar and GPIO ports
205 //
206 void PORT_Init (void)
207 {
208 1
209 1 IT01CF = 0x03; // Enable Interrupt 0 on P0.3
210 1 TCON &= ~0x01; // Make /INT0 level triggered
211 1
212 1 XBR0 = 0x01; // Enable UART on P0.4(TX) and P0.5(RX)
213 1 XBR1 = 0x40; // Enable crossbar and enable
214 1 // weak pull-ups
215 1
216 1 P0MDOUT |= 0x10; // enable UTX as push-pull output
217 1 P1MDOUT |= 0xD8; // /WR and /RD are push-pull
218 1 // AB4 LEDs are push-pull
219 1 P2MDOUT |= 0xFF;
220 1 P3MDOUT |= 0xFF;
221 1 P4MDOUT |= 0xFF;
222 1
223 1 }
224
225 //-----------------------------------------------------------------------------
226 // EMIF_Init
227 //-----------------------------------------------------------------------------
228 //
229 // Configure the External Memory Interface for both on and off-chip access.
230 //
231 void EMIF_Init (void)
232 {
233 1
234 1 EMI0CF = 0x1B; // non-muxed mode; split mode
235 1 // with bank select
236 1
237 1 EMI0TC = EMIF_TIMING; // This constant may be modified
238 1 // according to SYSCLK to meet the
239 1 // timing requirements for the CP2200
240 1
C51 COMPILER V8.08 MAIN 04/01/2008 20:10:55 PAGE 5
241 1 EMI0CN = BASE_ADDRESS; // Page of XRAM accessed by EMIF
242 1
243 1 }
244
245 //-----------------------------------------------------------------------------
246 // SYSCLK_Init
247 //-----------------------------------------------------------------------------
248 //
249 // This routine initializes the system clock.
250 //
251 void SYSCLK_Init (void)
252 {
253 1 int i;
254 1
255 1 OSCICN |= 0x03; // Configure internal oscillator for
256 1 // its maximum frequency
257 1
258 1 CLKMUL = 0x00; // Reset Clock Multiplier and select
259 1 // internal oscillator as input source
260 1
261 1 CLKMUL |= 0x80; // Enable the Clock Multiplier
262 1
263 1 for(i = 0; i < 256; i++); // Delay at least 5us
264 1
265 1 CLKMUL |= 0xC0; // Initialize the Clock Multiplier
266 1
267 1 while(!(CLKMUL & 0x20)); // Wait for MULRDY => 1
268 1
269 1 RSTSRC = 0x06; // Enable missing clock detector
270 1 // and VDD monitor
271 1
272 1 FLSCL |= 0x10; // Set Flash Scale for 48MHz
273 1
274 1 CLKSEL |= 0x03; // Select output of clock multiplier
275 1 // as the system clock.
276 1
277 1 }
278
279 //-----------------------------------------------------------------------------
280 // ether_reset_low
281 //-----------------------------------------------------------------------------
282 //
283 // This routine drives the reset pin of the ethernet controller low.
284 //
285 void ether_reset_low()
286 {
287 1
288 1 P1 &= ~0x01; // Pull reset low
289 1
290 1 }
291
292 //-----------------------------------------------------------------------------
293 // ether_reset_high
294 //-----------------------------------------------------------------------------
295 //
296 // This routine places the reset pin in High-Z allowing it to be pulled up
297 // using the external pull-up resistor.
298 //
299 // Additionally, this routine waits for the reset pin to read high before
300 // exiting.
301 //
302 void ether_reset_high (void)
C51 COMPILER V8.08 MAIN 04/01/2008 20:10:55 PAGE 6
303 {
304 1
305 1 P1 |= 0x01; // Allow /RST to rise
306 1 while(!(P1 & 0x01)); // Wait for /RST to go high
307 1
308 1
309 1 }
C51 COMPILATION COMPLETE. 0 WARNING(S), 1 ERROR(S)
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